Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

  • State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 101 subscribers
  • Views 126 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5706: About the reset circuit of AM57x

O.H
Genius 5795 points
Part Number: AM5706

Hi experts,

Currently my customer is starting to design a circuit with a combination of AM5706 and TPS659163. They are referring to the schematic of TMDSEVM572(and TMDXIDK574), but there are some unclear points, so please let me check them.

1) About resetn/porz

According to the power-up sequencing in the datasheet, resetn/porz are supposed to start up at the same time. However, based on the circuit diagram, resetn goes "H" when VDD_3V3_SP is activated and CPU_RESETn is released, thus releasing the SoC RESET. At this time, porz and resetn are not synchronized in TMDSEVM572.
From the note (7) in the datasheet, does it mean that there is no problem if resetn rises after VDD_3V3_SP and porz rises after that?

2) About rstoutn

In the TMDSEVM572, rstoutn is set to "H", and this signal controls the porz of the SoC. According to the power-up sequencing in the datasheet, porz should operate before rstoutn, which causes a contradiction.
Could you please tell me how this works?

3) About WARM RESET

As for the WARM RESET circuit, since we are planning to start up with power-on reset, is there any problem if we delete this circuit?

4) About the reset circuit of the TMDXIDK574

The SoC's RSTOUTn output signal (AM57XX_RSTOUTn) is input to the SoC's RESETn through a buffer.
I haven't seen many circuits where the SoC controls the reset of the SoC, so could you please tell me about it?

Best regards,
O.H

  • 0
    TI__Mastermind 46000 points

    1).  There is no specific timing relationship/requirement between RESETN and PORz.  If RESETN is unused, it can be pulled up - which means it is de-asserted prior to PORz de-assertion.  This is expected.

    3)  There is an errata item that states warm reset can cause issues, and recommends power-on reset to clear.  I believe the circuit forces any warm reset to generate PORz.

  • 0 in reply to Robert Eschler
    Genius 5795 points

    Hello,

    Thank you for your quick answer. I understand about 1), and I will check about 3), including the errata.

    I would appreciate it if you could answer 2) and 4) as well.

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Mastermind 46000 points

    For #2, I believe the circuit shown provides a delay between RSTOUTn and PORz.  As previously mentioned, the errata item states that any internal reset conditions needs to be cleared with a PORz.  The RSTOUTn is asserted with internal reset, and the delay circuit then creates the PORz.  I a believe the circuit (or something similar) is need to avoid reset loop condition, where the device is stuck in reset.

    For #4, the buffer referenced on RSTOUTn is DNI (Do Not Install), thus it is not used.  The signal connects directly to PMIC warm reset input.  This is the recommended configuration.