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Unhandled Exception in EL3

Embedded Eng.
Prodigy 130 points
Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

Hi,

I have a custom board with XAM6442ASFGGAALV as CPU.

I'm having crashes in U-boot + Linux.

For example, If I try to read 0x43002200 address in U-boot:

=> md 0x43002200
43002200: 4cf980b8 0000f484Unhandled Exception in EL3.
x30            = 0x00000000701a0e2c
x0             = 0x00000000bffb6000
x1             = 0x0000000000000000
x2             = 0x0000000000000034
x3             = 0x0000000000000002
x4             = 0x0000000043002208
x5             = 0x00000000bdecea08
x6             = 0x00000000bffb62dc
x7             = 0x0000000000000004
x8             = 0x00000000bdecf078
x9             = 0x0000000000000008
x10            = 0x00000000ffffffd8
x11            = 0x0000000000000010
x12            = 0x0000000000000006
x13            = 0x000000000001869f
x14            = 0x00000000bdecf440
x15            = 0x0000000000000021
x16            = 0x00000000bff5838c
x17            = 0x0000000000000000
x18            = 0x00000000bded8de0
x19            = 0x0000000000000040
x20            = 0x0000000043002200
x21            = 0x0000000043002200
x22            = 0x00000000bffb55dd
x23            = 0x0000000000000008
x24            = 0x0000000000000009
x25            = 0x0000000000000004
x26            = 0x0000000000000004
x27            = 0x00000000bdecf138
x28            = 0x0000000000000004
x29            = 0x00000000bdecf0b0
scr_el3        = 0x000000000000073d
sctlr_el3      = 0x0000000030cd183f
cptr_el3       = 0x0000000000000000
tcr_el3        = 0x0000000080803520
daif           = 0x00000000000002c0
mair_el3       = 0x00000000004404ff
spsr_el3       = 0x00000000600003c9
elr_el3        = 0x00000000bff972a0
ttbr0_el3      = 0x00000000701ad6c0
esr_el3        = 0x0000000092000010
far_el3        = 0x0000000043002208
spsr_el1       = 0x0000000000000000
elr_el1        = 0x0000000000000000
spsr_abt       = 0x0000000000000000
spsr_und       = 0x0000000000000000
spsr_irq       = 0x0000000000000000
spsr_fiq       = 0x0000000000000000
sctlr_el1      = 0x0000000030d00801
actlr_el1      = 0x0000000000000000
cpacr_el1      = 0x0000000000000000
csselr_el1     = 0x0000000000000000
sp_el1         = 0x0000000000000000
esr_el1        = 0x0000000000000000
ttbr0_el1      = 0x0000000000000000
ttbr1_el1      = 0x0000000000000000
mair_el1       = 0x0000000000000000
amair_el1      = 0x0000000000000000
tcr_el1        = 0x0000000000800080
tpidr_el1      = 0x0000000000000000
tpidr_el0      = 0x0000000000000000
tpidrro_el0    = 0x0000000000000000
par_el1        = 0x0000000000000000
mpidr_el1      = 0x0000000080000000
afsr0_el1      = 0x0000000000000000
afsr1_el1      = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1       = 0x0000000000000000
cntp_ctl_el0   = 0x0000000000000000
cntp_cval_el0  = 0xe863004477c58bf9
cntv_ctl_el0   = 0x0000000000000002
cntv_cval_el0  = 0x7dd7db5990287d31
cntkctl_el1    = 0x0000000000000000
sp_el0         = 0x0000000000000000
isr_el1        = 0x0000000000000000
dacr32_el2     = 0x0000000000000000
ifsr32_el2     = 0x0000000000000000
cpuectlr_el1   = 0x0000000000000040
cpumerrsr_el1  = 0x00000000110006b7
l2merrsr_el1   = 0x00000000123412e0
cpuactlr_el1   = 0x00001000090ca000

Seems that the error comes when U-boot tries to read the third address (0x43002208)

=> md 0x43002208
43002208:Unhandled Exception in EL3.
x30            = 0x00000000701a0e2c
x0             = 0x0000000000000009
x1             = 0x0000000000000000
x2             = 0x000000000000003a
x3             = 0x0000000000000000
x4             = 0x0000000043002208
x5             = 0x00000000bdecea08
x6             = 0x00000000bffb62dc
x7             = 0x0000000000000004
x8             = 0x00000000bdecf078
x9             = 0x0000000000000008
x10            = 0x00000000ffffffd0
x11            = 0x0000000000000010
x12            = 0x0000000000000006
x13            = 0x000000000001869f
x14            = 0x00000000bdecf440
x15            = 0x0000000000000021
x16            = 0x00000000bff5838c
x17            = 0x0000000000000000
x18            = 0x00000000bded8de0
x19            = 0x0000000000000040
x20            = 0x0000000043002208
x21            = 0x0000000043002208
x22            = 0x00000000bffb55dd
x23            = 0x0000000000000008
x24            = 0x0000000000000009
x25            = 0x0000000000000004
x26            = 0x0000000000000004
x27            = 0x00000000bdecf138
x28            = 0x0000000000000004
x29            = 0x00000000bdecf0b0
scr_el3        = 0x000000000000073d
sctlr_el3      = 0x0000000030cd183f
cptr_el3       = 0x0000000000000000
tcr_el3        = 0x0000000080803520
daif           = 0x00000000000002c0
mair_el3       = 0x00000000004404ff
spsr_el3       = 0x00000000600003c9
elr_el3        = 0x00000000bff972a0
ttbr0_el3      = 0x00000000701ad6c0
esr_el3        = 0x0000000092000010
far_el3        = 0x0000000043002208
spsr_el1       = 0x0000000000000000
elr_el1        = 0x0000000000000000
spsr_abt       = 0x0000000000000000
spsr_und       = 0x0000000000000000
spsr_irq       = 0x0000000000000000
spsr_fiq       = 0x0000000000000000
sctlr_el1      = 0x0000000030d00801
actlr_el1      = 0x0000000000000000
cpacr_el1      = 0x0000000000000000
csselr_el1     = 0x0000000000000000
sp_el1         = 0x0000000000000000
esr_el1        = 0x0000000000000000
ttbr0_el1      = 0x0000000000000000
ttbr1_el1      = 0x0000000000000000
mair_el1       = 0x0000000000000000
amair_el1      = 0x0000000000000000
tcr_el1        = 0x0000000000800080
tpidr_el1      = 0x0000000000000000
tpidr_el0      = 0x0000000000000000
tpidrro_el0    = 0x0000000000000000
par_el1        = 0x0000000000000000
mpidr_el1      = 0x0000000080000000
afsr0_el1      = 0x0000000000000000
afsr1_el1      = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1       = 0x0000000000000000
cntp_ctl_el0   = 0x0000000000000000
cntp_cval_el0  = 0xe863044477cd83fb
cntv_ctl_el0   = 0x0000000000000002
cntv_cval_el0  = 0x7dc7d95980287d31
cntkctl_el1    = 0x0000000000000000
sp_el0         = 0x0000000000000000
isr_el1        = 0x0000000000000000
dacr32_el2     = 0x0000000000000000
ifsr32_el2     = 0x0000000000000000
cpuectlr_el1   = 0x0000000000000040
cpumerrsr_el1  = 0x00000000111c06b1
l2merrsr_el1   = 0x0000000012241260
cpuactlr_el1   = 0x00001000090ca000

This happens in many addresses.

The same happens in Linux:

# devmem 0x43002208
Unhandled Exception in EL3.
x30            = 0x00000000701a0e2c
x0             = 0x0000ffff7f740000
x1             = 0x0000000000002208
x2             = 0x0000000000000000
x3             = 0x0000000000000001
x4             = 0x0000000000000003
x5             = 0x0000000043000000
x6             = 0x0000000000000000
x7             = 0x0000ffff7f85b210
x8             = 0x00000000000000de
x9             = 0x000000000000000f
x10            = 0x0101010101010101
x11            = 0x0000000000000020
x12            = 0x0000000000000000
x13            = 0x0000ffff7f753e30
x14            = 0x00000000000003f3
x15            = 0x0000ffff7f750aa0
x16            = 0x0000ffff7f81a250
x17            = 0x00000000004c3a28
x18            = 0x0000000000000001
x19            = 0x0000000000000020
x20            = 0x0000000000002208
x21            = 0x00000000004c3000
x22            = 0x0000ffffca6f5dd0
x23            = 0x0000000043002208
x24            = 0x0000000000000000
x25            = 0x0000000000000000
x26            = 0x0000000000000000
x27            = 0x0000000000000000
x28            = 0x0000000000000000
x29            = 0x0000ffffca6f5c90
scr_el3        = 0x000000000000073d
sctlr_el3      = 0x0000000030cd183f
cptr_el3       = 0x0000000000000000
tcr_el3        = 0x0000000080803520
daif           = 0x00000000000002c0
mair_el3       = 0x00000000004404ff
spsr_el3       = 0x0000000060000000
elr_el3        = 0x000000000041523c
ttbr0_el3      = 0x00000000701ad6c0
esr_el3        = 0x0000000092000010
far_el3        = 0x0000ffff7f742208
spsr_el1       = 0x0000000040000000
elr_el1        = 0x0000ffff7f81a26c
spsr_abt       = 0x0000000000000000
spsr_und       = 0x0000000000000000
spsr_irq       = 0x0000000000000000
spsr_fiq       = 0x0000000000000000
sctlr_el1      = 0x0000000034d4d91d
actlr_el1      = 0x0000000000000000
cpacr_el1      = 0x0000000000300000
csselr_el1     = 0x0000000000000000
sp_el1         = 0xffff800015010000
esr_el1        = 0x0000000056000000
ttbr0_el1      = 0x000000008f0b2200
ttbr1_el1      = 0x00b0000081640000
mair_el1       = 0x000c0400bb44ffff
amair_el1      = 0x0000000000000000
tcr_el1        = 0x00000032f5d07590
tpidr_el1      = 0xffff80002ed10000
tpidr_el0      = 0x0000ffff7f9536d0
tpidrro_el0    = 0x0000000000000000
par_el1        = 0x0000000000000000
mpidr_el1      = 0x0000000080000000
afsr0_el1      = 0x0000000000000000
afsr1_el1      = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1       = 0xffff800010010800
cntp_ctl_el0   = 0x0000000000000005
cntp_cval_el0  = 0x0000000160e2401c
cntv_ctl_el0   = 0x0000000000000002
cntv_cval_el0  = 0x7dd7db49802c7c71
cntkctl_el1    = 0x00000000000000d6
sp_el0         = 0x0000ffffca6f5ba0
isr_el1        = 0x0000000000000040
dacr32_el2     = 0x0000000000000000
ifsr32_el2     = 0x0000000000000000
cpuectlr_el1   = 0x0000000000000040
cpumerrsr_el1  = 0x0000000011080557
l2merrsr_el1   = 0x00000000122412e0
cpuactlr_el1   = 0x00001000090ca000

This exception occurs during memtester as well:

# memtester 100MB > /dev/null &
[1] 182
# memtester 100MB > /dev/null &
[2] 183
# Unhandled Exception in EL3.
x30            = 0x00000000701a0e2c
x0             = 0x0000000000000000
x1             = 0x7c00c3003f005000
x2             = 0x3ff950207cf7c320
x3             = 0x0000000001a4c978
x4             = 0x3ff950207cf7c320
x5             = 0x000000000063f001
x6             = 0x0000ffffa4e38008
x7             = 0x0000ffffa8030010
x8             = 0x3ffb52a17cf7fba0
x9             = 0x0000000000000001
x10            = 0x000000007ffffff2
x11            = 0x0000000000000000
x12            = 0x0000000000000000
x13            = 0x0000000000000015
x14            = 0x0000000000000001
x15            = 0x0000000000000000
x16            = 0x0000000000415040
x17            = 0x0000ffffa8076aa0
x18            = 0x00000000031ffff8
x19            = 0x000000000034992f
x20            = 0x0000ffffa368c978
x21            = 0x0000ffffa6884980
x22            = 0x000000000063f001
x23            = 0x0000000000403610
x24            = 0x0000000000415000
x25            = 0x0000000000415240
x26            = 0x0000000000000000
x27            = 0x000000000063f001
x28            = 0x0000000000000001
x29            = 0x0000ffffeb133590
scr_el3        = 0x000000000000073d
sctlr_el3      = 0x0000000030cd183f
cptr_el3       = 0x0000000000000000
tcr_el3        = 0x0000000080803520
daif           = 0x00000000000002c0
mair_el3       = 0x00000000004404ff
spsr_el3       = 0x0000000080000000
elr_el3        = 0x00000000004017dc
ttbr0_el3      = 0x00000000701ad6c0
esr_el3        = 0x0000000092000010
far_el3        = 0x0000000000415240
spsr_el1       = 0x0000000020000000
elr_el1        = 0x00000000004017d4
spsr_abt       = 0x0000000000000000
spsr_und       = 0x0000000000000000
spsr_irq       = 0x0000000000000000
spsr_fiq       = 0x0000000000000000
sctlr_el1      = 0x0000000034d4d91d
actlr_el1      = 0x0000000000000000
cpacr_el1      = 0x0000000000300000
csselr_el1     = 0x0000000000000000
sp_el1         = 0xffff800015130000
esr_el1        = 0x0000000056000000
ttbr0_el1      = 0x000000008ffc2400
ttbr1_el1      = 0x00b0000081640000
mair_el1       = 0x000c0400bb44ffff
amair_el1      = 0x0000000000000000
tcr_el1        = 0x00000032f5d07590
tpidr_el1      = 0xffff80002ed10000
tpidr_el0      = 0x0000ffffa82130c0
tpidrro_el0    = 0x0000000000000000
par_el1        = 0x0000000000000000
mpidr_el1      = 0x0000000080000000
afsr0_el1      = 0x0000000000000000
afsr1_el1      = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1       = 0xffff800010010800
cntp_ctl_el0   = 0x0000000000000005
cntp_cval_el0  = 0x000000015fed0acf
cntv_ctl_el0   = 0x0000000000000002
cntv_cval_el0  = 0x7d47d9598028fd71
cntkctl_el1    = 0x00000000000000d6
sp_el0         = 0x0000ffffeb133590
isr_el1        = 0x0000000000000040
dacr32_el2     = 0x0000000000000000
ifsr32_el2     = 0x0000000000000000
cpuectlr_el1   = 0x0000000000000040
cpumerrsr_el1  = 0x00000000111805d7
l2merrsr_el1   = 0x00000000122032e0
cpuactlr_el1   = 0x00001000090ca000

This always happens during memtester, sometimes after a few seconds and sometimes after a few minutes.

I'm not sure if this is a DDR training issue or some wrong parameter (memory base address etc..)

My board has 1GB DDR memory K4A8G165WC-BITD000.

I used TI's DDR configuration tool to generate a dtsi file, which is included in the R5 device-tree file.

Here is the output syscfg file:

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --product "Processor_DDR_Config@0.08.00"
 * @versions {"tool":"1.9.0+2015","templates":null}
 */

/**
 * Import the modules used in this configuration.
 */
const DDRSS = scripting.addModule("/DDRSS");

/**
 * Write custom configuration values to the imported modules.
 */
DDRSS.ddr4.$name                         = "ddr4_DDRSS_DDR40";
DDRSS.ddr4.system_cfg_dram_density       = 8;
DDRSS.ddr4.config_dram_tCCD_L_tCK        = 5;
DDRSS.ddr4.config_dram_tCCD_L_ns         = 6.25;
DDRSS.ddr4.config_dram_tPAR_ALERT_PW_tCK = 96;
DDRSS.ddr4.config_dram_tDQSCKmin_ns      = 0.225;
DDRSS.ddr4.config_dram_tDQSCKmax_ns      = 0.225;
DDRSS.ddr4.config_dram_tFAW_ns           = 35;
DDRSS.ddr4.config_dram_tRRD_L_ns         = 7.5;
DDRSS.ddr4.config_dram_tRRD_S_ns         = 6;
DDRSS.ddr4.config_dram_mr0_cl            = 11;

I changed the memory sections in all device tree files:

U-boot R5 memory section in device tree:

        memory@80000000 {
                device_type = "memory";
                /* 1G RAM */
                reg = <0x00000000 0x80000000 0x00000000 0x40000000>;

        };

        a53_0: a53@0 {
                compatible = "ti,am654-rproc";
                reg = <0x00 0x00a90000 0x00 0x10>;
                power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
                                <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
                resets = <&k3_reset 135 0>;
                clocks = <&k3_clks 61 0>;
                assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
                assigned-clock-parents = <&k3_clks 61 2>;
                assigned-clock-rates = <200000000>, <1000000000>;
                ti,sci = <&dmsc>;
                ti,sci-proc-id = <32>;
                ti,sci-host-id = <10>;
                u-boot,dm-spl;
        };

        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;

                secure_ddr: optee@9e800000 {
                        reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
                        alignment = <0x1000>;
                        no-map;
                };
        };

U-boot A53 memory section in device tree:

        memory@80000000 {
                device_type = "memory";
                /* 1G RAM */
                reg = <0x00000000 0x80000000 0x00000000 0x40000000>;

        };

        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;

                secure_ddr: optee@9e800000 {
                        reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
                        alignment = <0x1000>;
                        no-map;
                };
        };

Linux memory section in device tree:

	memory@80000000 {
		device_type = "memory";
		/* 1G RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;

	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
			alignment = <0x1000>;
			no-map;
		};

		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3100000 0x00 0xf00000>;
			no-map;
		};

		rtos_ipc_memory_region: ipc-memories@a5000000 {
			reg = <0x00 0xa5000000 0x00 0x00800000>;
			alignment = <0x1000>;
			no-map;
		};
	};

DDR init funcions in U-boot (board directory)

int dram_init(void)
{
        gd->ram_size = 0x40000000;
        return 0;
}

int dram_init_banksize(void)
{
        /* Bank 0 declares the memory available in the DDR low region */
        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
        gd->bd->bi_dram[0].size = 0x40000000;
        gd->ram_size = 0x40000000;

        return 0;
}

(CONFIG_SYS_SDRAM_BASE = 0x80000000 )

DDR size message during U-boot:

DRAM: 1 GiB

Memory size from Linux:

# free -m
              total        used        free      shared  buff/cache   available
Mem:            906          56         754          95          95         690
Swap:             0           0           0

My code is based on 08.00.00.004 SDK vesrion.

I could use some help solving this issue.

Thanks.

  • 0
    TI__Mastermind 27050 points

    I think there are two different issues here. Reading the control register area at 0x43002208  and the the DDR test with memtester. The Ethernet MAC is readable at 0x43002200 for the low bits and 0x43002204 for the high bits. 0x43002208 is a reserved memory area in the TRM. This should have nothing to do with DDR, and in general I would not do bulk reads of configuration register space that is reserved in the memory map.

    The DDR memtester failures would point to a memory setting and/or board level issue. It looks like DDR4 (not LPDDR4).

  • 0 in reply to Pekka Varis
    Prodigy 130 points

    Thanks,

    So the exception while reading the control register is expected?

    Regarding the memtester, can you point me to the relevant code parts?

    What should I configure other than the dtsi file included the U-boot R5 device tree (DDR configuration tool output), RAM size/base address in U-boot init functions, and RAM size/base address in device tree?

    Thanks again.

  • 0 in reply to Embedded Eng.
    TI__Mastermind 27050 points
    Embedded Eng. said:
    So the exception while reading the control register is expected?

    Yes. Unfortunately the control MMR space and the "holes" or reserved addresses there trigger a system abort even on a read. So one must be careful to only read well defined registers. If you want to just test reading something other than DDR, for example MSRAM at 0x0700c0000 could make sense.

    Embedded Eng. said:
    What should I configure other than the dtsi file included the U-boot R5 device tree (DDR configuration tool output), RAM size/base address in U-boot init functions, and RAM size/base address in device tree?

    On first look I did not see anything jump out in the configuration. But there are many registers in the DDR controller and phy. Have you tried with a DDR4 configuration at a lower speed? Also are you contact with an FAE who would have helped you with a schematics review?

  • 0 in reply to Pekka Varis
    Mastermind 7560 points

    Hello Pekka,

    we've seen these "Unhandled Exception in EL3" now and then, too, and it was always a bug in some driver code that accessed a memory location it shouldn't have accessed, but I'm wondering if it is really intentional that these faults lead to a panic in the ATF (at least I think that's where the message comes from).

    Do you know why these exceptions are passed all the way to ATF?

    I have to admit that I never looked into this long enough to understand what's going on, because eventually we figured out what our actual problem was, but these exceptions make debugging pretty difficult.

    Regards,

    Dominic

  • 0 in reply to Dominic Rath
    TI__Mastermind 27050 points
    Dominic Rath said:

    Do you know why these exceptions are passed all the way to ATF?

    I have to admit that I never looked into this long enough to understand what's going on, because eventually we figured out what our actual problem was, but these exceptions make debugging pretty difficult.

    You are correct this is passed all the way to ATF. The quick guidance from our team was for debug to disable the exception in ATF to allow to examination of what happened. I don't have a pointer to how to do that yet.

    The history behind the abort is maybe best summarized that the read to the non-existent memory location in some of the MMR spaces does not return with a typical value like zero to the reader but instead only triggers the abort. This is a feature of the bus protocol used. Which is quite unfortunate for debug purposes.

      Pekka

  • 0 in reply to Pekka Varis
    Prodigy 130 points

    Hi,

    Our HW design was reviewed by TI team.

    I tried lower speed and still had failures.

    I tried multiple Nominal ODT (RttNOM) values in the DDR config tool,

    Some values leads to memtester failuers after a few seconds, and some values leads to EL3 exceptions (without memtester failures).

    Is this possible that the EL3 exceptions are caused because Linux tries to access reserves spaces (which trigger a system abort) ?

    Maybe error in the memory map?

    Can you recommend me another debug steps?

  • 0 in reply to Embedded Eng.
    TI__Mastermind 27050 points

    I think the control MMR reserved area read EL3 exception is unrelated, unfortunate feature of the internal memory bus. The DDR4 memtester issues, I'm forwarding this to the specialists in that area.

      Pekka

  • 0 in reply to Pekka Varis
    Prodigy 130 points

    OK, thanks.

    I just want to update that I tried all    Output Driver Impedance (ODI)/Nominal ODT (RttNOM)  combinations, and had bit flips/Linux crashes in all of them.

  • 0 in reply to Embedded Eng.
    TI__Guru* 89485 points

    Alvaro, can you try with the dtsi attached

    I took your sysconfig file and enabled Read DBI.  We are finding that this is necessary to enable Read DBI on DDR4 designs to avoid resonance issues in the DDR IO supply.  it will also improve the power consumption of the memory itself

    /cfs-file/__key/communityserver-discussions-components-files/791/k3_2D00_am64_2D00_ddr_2D00_config_5F00_RD_5F00_DBI.dtsi

    REgards,

    James

  • 0 in reply to JJD
    Prodigy 130 points

    Running memtester for 1 hour with your DTSI, no errors for now, Thanks!

    Can you send me the syscfg file as well?

    I could not find the DBI option in the ddr configuration tool, how is it called?

  • 0 in reply to Embedded Eng.
    TI__Guru* 89485 points

    Hi Alvaro, that is good news!  Please run for longer on several boards if possible to ensure robustness.

    Yes, the DBI option is not available in the publicly released syscfg tool (i enabled it internally to generate your configuration).  The DBI option will be available in the next public release, should be in the next week or so. Will let you know  

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 130 points

    I had no errors in 15+- hours for now.

    I'm going to run memtester all weekend.

    I will update if I get errors.

    I have a question regarding the DBI solution.

    Let's assume the worst case scenario, read of the combination 10101010 - 01010101 repeatedly for a long time (10101010, 01010101,10101010, 01010101,10101010, 01010101...), the bytes won't be inverted, so, in this case, the DBI won't do anything.

    So, in this case, I will have the same errors I had without enabling the DBI.

    Am I wrong?

  • 0 in reply to Embedded Eng.
    TI__Guru* 89485 points

    That is good news., Yes continue the tests and let me know the results.

    Yes, this is a good question.  That pattern is the worst case switching pattern with read DBI enabled, but from a current consumption perspective does not cross into the threshold that can start affecting the DDR IO supply significantly.  The affect of the data pattern is also dependent on the switching frequency, and the highest switching frequency may not always be the worst case.  So enabling DBI helps on a couple of fronts to avoid the scenarios that can cause the errors.

    Regards,

    James

  • +1 in reply to JJD
    TI__Guru* 89485 points

    DDR register configuration tool with DBI setting (v8.1) is now available at dev.ti.com/sysconfig

    Regards,

    James