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AM5718: Timing settings for DE mode LCD

Part Number: AM5718

Hi, we are driving DE mode LCD. In Linux, we see below configuration need to set. It seems that these parameters are for hysnc/vsync mode LCD. Our question is where to set for DE LCD? If there is no other place to set, how to convert the LCD's DE timing requirment to hysnc/vsync? Is it  hfront-porch + hback-porch +hsync-len = DE inactive duration? The LCD DE timing spec also attached below. 

display-timing bindings

=======================

 

display-timings node

--------------------

 

required properties:

- none

 

optional properties:

- native-mode: The native mode for the display, in case multiple modes are

             provided. When omitted, assume the first node is the native.

 

timing subnode

--------------

 

required properties:

- hactive, vactive: display resolution

- hfront-porch, hback-porch, hsync-len: horizontal display timing parameters

   in pixels

   vfront-porch, vback-porch, vsync-len: vertical display timing parameters in

   lines

- clock-frequency: display clock in Hz

 

optional properties:

- hsync-active: hsync pulse is active low/high/ignored

- vsync-active: vsync pulse is active low/high/ignored

- de-active: data-enable pulse is active low/high/ignored

- pixelclk-active: with

                    - active high = drive pixel data on rising edge/

                                 sample data on falling edge

                    - active low  = drive pixel data on falling edge/

                                 sample data on rising edge

                    - ignored     = ignored

- syncclk-active: with

                    - active high = drive sync on rising edge/

                                 sample sync on falling edge of pixel

                                 clock

                    - active low  = drive sync on falling edge/

                                 sample sync on rising edge of pixel

                                 clock

                    - omitted     = same configuration as pixelclk-active

- interlaced (bool): boolean to enable interlaced mode

- doublescan (bool): boolean to enable doublescan mode

- doubleclk (bool): boolean to enable doubleclock mode

 

All the optional properties that are not bool follow the following logic:

    <1>: high active

    <0>: low active

    omitted: not used on hardware

 

There are different ways of describing the capabilities of a display. The

devicetree representation corresponds to the one commonly found in datasheets

for displays. If a display supports multiple signal timings, the native-mode

can be specified.

 

The parameters are defined as:

 

 +----------+-------------------------------------+----------+-------+

  |          |        ^                            |          |       |

  |          |        |vback_porch                 |          |       |

  |          |        v                            |          |       |

  +----------#######################################----------+-------+

  |          #        ^                            #          |       |

  |          #        |                            #          |       |

  |  hback   #        |                            #  hfront  | hsync |

  |   porch  #        |       hactive              #  porch   |  len  |

  |<-------->#<-------+--------------------------->#<-------->|<----->|

  |          #        |                            #          |       |

  |          #        |vactive                     #          |       |

  |          #        |                            #          |       |

  |          #        v                            #          |       |

  +----------#######################################----------+-------+

  |          |        ^                            |          |       |

  |          |        |vfront_porch                |          |       |

  |          |        v                            |          |       |

  +----------+-------------------------------------+----------+-------+

  |          |        ^                            |          |       |

  |          |        |vsync_len                   |          |       |

  |          |        v                            |          |       |

  +----------+-------------------------------------+----------+-------+

 

Note: In addition to being used as subnode(s) of display-timings, the timing

      subnode may also be used on its own. This is appropriate if only one mode

      need be conveyed. In this case, the node should be named 'panel-timing'.

  • Hi,

    Our question is where to set for DE LCD?

    DE is by default output in the separate pin from DSS, when DSS is configured for discrete sync output. There is no separate configuration for getting DE output. We just need to make sure that pinmux for the DE pin is set up correctly and this pin is connected..

    If there is no other place to set, how to convert the LCD's DE timing requirment to hysnc/vsync?

    Timing for DE is based on the HS timing, ie it will remain active only during active portion of the line and inactive during blanking portion. So inactive during front porch + hsync lentgh + back porch.. 

    Regards,

    Brijesh

  • Hi Brijesh, thanks for your explanation. Still one question, in our case, do we still need to set each value in Linux for front porch , hsync lentgh,  back porch to make the sum equals the DE inactive time specified in LCD datasheet? my confusion is that if only via pinmux configuration, how does the processor control the inactive DE timing to accomodate to LCD spec?

  • Hi liao,

    Not sure about Linux, but typically, yes, all three components of the blanking period are exposed and needs to be provided to the driver. Driver will configure it to the DSS registers. Pinmux setting alone is not sufficient. 

    Regards,

    Brijesh