AM6411: IEEE1588 PTP implementation with 1pps

Sung-IL

Mastermind 31540 points

Part Number: AM6411

Dear Champs,

Is it possible to implement IEEE1588 PTP with 1PPS?

What my customer want to implement are

- generate 1PPS using Master OSC or External OSC

- Phase detect between external 1PPS input and generated 1PPS.

Can all these be implemented on AM64x?

Thanks and Best Regards,

SI.

over 4 years ago

+1 Pekka Varis over 4 years ago

TI__Mastermind 27050 points

SI,

Yes we support 1pps. Linux example of generating 1pps is documented in https://software-dl.ti.com/processor-sdk-linux/esd/docs/08_00_00_21/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW3g.html and if you search for "pulse per second" or "testptp". The 1588 stack based on ptp4l will run out of the box, the helper program testptp looks like is not part of the filesystem by default. For 1 pps example you will need to get testptp program and follow the examples.

Pekka

0 Sung-IL over 4 years ago in reply to Pekka Varis

TI__Mastermind 31540 points

Hi Pekka,

Thanks for the immediate response.

My customer is looking for the platform to implement IEEE1588 PTP application with 1G ethernet and is checking AM335x now.

Could you please let me know what is improved in AM64x compared with AM335x in aspect to implement IEEE1588 PTP?

Do you think 'Phase detect' can be implemented on both of AM64x and AM335x? If so, how it can be implemented?

I'm not familiar with IEEE1588 and please let me know your idea.

When I checked linux ptp implementation on AM335x, it seems it is implemented only on PRU, not CPSW, right?

And also, it seems there is still pps offset issue in the AM335x and there is no improvement when I checked latest linux SDK UG(7.3).

Is this only limitation in AM335x to implement IEEE1588 PTP?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/835024/ccs-am3358-ptp-1pps-question/3090668?tisearch=e2e-sitesearch&keymatch=am335x%252525252525252520AND%252525252525252520ptp%252525252525252520AND%252525252525252520CPSW#3090668

Known Issue: On AM335x/AM437x, the current PPS implementation has the possibility of failing to correctly synchronize PPS output to a master (only the PPS output is affected, the PTP functionality still succeeds). This appears as the slave PPS being offset from the master PPS signal on an order of 40-100ms either on starting PPS or after running for an extended period of time. As a workaround, if PPS output is observed to be offset, then to temporarily stabilize PPS output for measurement, bring down and then bring back up the ethernet interface in use to reset PTP/PPS (e.g. ifconfig eth1 down/ifconfig eth1 up). If the PPS output is successful, then the output is valid and can be used to measure jitter.

Thanks and Best Regards,

SI.

+1 Pekka Varis over 4 years ago in reply to Sung-IL

TI__Mastermind 27050 points

Sung-IL said:
Is this only limitation in AM335x to implement IEEE1588 PTP?

AM335x supports IEEE1588v1 or as it is more accurately called IEEE1588-2002. The 1588v2 or IEEE1588-2008 is not supported on AM335x. See https://e2e.ti.com/support/processors-group/processors/f/processors-forum/798470/am3352-ieee-1588v2-annex-d-time-stamping-limitations for more background.

AM64x supports 1588-2008 and 802.1AS-2011 with the software available today on CPSW3G and ICSSG based Ethernet, and the hardware is 802.1AS-2020 capable. The examples using linuxptp and ptp4l are 802.1AS-2011, as the 2020 version support is not yet included in linuxptp. And AM64x supports pps generation with the hardware CPTS and ICSSG sync and latch.

Pekka

0 Sung-IL over 4 years ago in reply to Pekka Varis

TI__Mastermind 31540 points

Hi Pekka,

Thanks for your response.

Do you have any idea how 'Phase detect' can be implemented on AM64x between generated 1PPS and external 1PPS input to sync OSC to this 1PPS?

Thanks and Best Regards,

SI.

+1 Pekka Varis over 4 years ago in reply to Sung-IL

TI__Mastermind 27050 points

Thanks to some help from a colleague I'm guessing "phase detect" means capturing the difference between two pps signals, one constructed from 1588, and another that is available on a pin. The ICSSG IEP latch and the CPSW3G CPTS push are meant for this. They both take a snapshot of the local counter used to generate a pps when an external pin toggled. The section "PPS Pulse Per Second support" at the link https://software-dl.ti.com/processor-sdk-linux/esd/docs/08_00_00_21/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW3g.html is exactly this. So you'd configure the external pps to be routed with the timesync router to the hw_push of CPTS used with 1588 PTP (or if using ICSS then the IEP latch) and the phase difference would be captured.

We don't have an example of this but the Linux documentation on CPSW3G and linuxptp is closest we have.

Pekka

0 Sung-IL over 4 years ago in reply to Pekka Varis

TI__Mastermind 31540 points

Hi Pekka,

Thanks for your response.

My customer is still investigating on AM64x and AM335x now.

Is there any way to implement IEEE1588v2 in AM335x?

In the e2e you mentioned for IEEE1588v2 implementation issue in AM335x, it seemed there are a Ethernet PHY to support time-stamping. With these PHY, IEEE1588v2 can be implemented on AM335x? or is there any way to implement it on AM335x?

Thanks and Best Regards,

SI.

+1 Pekka Varis over 4 years ago in reply to Sung-IL

TI__Mastermind 27050 points

Sung-IL said:
In the e2e you mentioned for IEEE1588v2 implementation issue in AM335x, it seemed there are a Ethernet PHY to support time-stamping. With these PHY, IEEE1588v2 can be implemented on AM335x? or is there any way to implement it on AM335x?

Yes. If you use a Ethernet PHY chip for the 1588 timestamps, all the 1588 capability is based on the PHY chip features. The IEEE1588v2 or more accurately IEEE1588-2008 requires timestamps to be captures for multicast frames, so as long as that support is there in the PHY the processor restrictions won't matter.

Pekka

0 Sung-IL over 4 years ago in reply to Pekka Varis

TI__Mastermind 31540 points

Hi Pekka,

Do you have any idea if linux ptp stack included in AM335x SDK can support IEEE1588v2 when Ethernet PHY TS was used?

Or, should customer implement it by themselves?

Thanks and Best Regards,

SI.

+1 Pekka Varis over 4 years ago in reply to Sung-IL

TI__Mastermind 27050 points

Sung-IL said:
Do you have any idea if linux ptp stack included in AM335x SDK can support IEEE1588v2 when Ethernet PHY TS was used?

Or, should customer implement it by themselves?

The Linux driver provided by the PHY vendor like TI should include this. TI PHY driver details are at https://www.ti.com/tool/ETHERNET-SW . Underneath the 1588 timestamps are read from the PHY, instead of reading them from the MAC like it is with Sitara.

Pekka

0 Sung-IL over 4 years ago in reply to Pekka Varis

TI__Mastermind 31540 points

Thanks Pekka,

Pekka Varis said:
The Linux driver provided by the PHY vendor like TI should include this. TI PHY driver details are at https://www.ti.com/tool/ETHERNET-SW . Underneath the 1588 timestamps are read from the PHY, instead of reading them from the MAC like it is with Sitara.

When Linux PHY driver was used for 1588 TS, do you think there is no modification required for 1588v2 even in PTP block in below?

I captured this block diagram from AM335x SDK UG.

How about ptp4l included in AM335x SDK? As ptp4l is open source, it should support IEEE1588v2, right?

Thanks and Best Regards,

SI.

+1 Pekka Varis over 4 years ago in reply to Sung-IL

TI__Mastermind 27050 points

The AM335x Linux HSR implementation using ICSSM with cut thru switching and duplicate removal is not part of upstream Linux. It will need some modification to support PHY with 1588 timestamps. The changes might be relatively straightforward, as it is just about where to read the timestamp associated with a received or sent 1588 packet.

Standard IEEE802.1Q Ethernet using upstream drivers is where this should be covered by the PHY driver.

Pekka

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AM6411: IEEE1588 PTP implementation with 1pps