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AM5706: PCIe Reset Specifications Not Met

Mari Tsunoda
Expert 5726 points

Part Number: AM5706

Hi,

Our customer is having issues with satisfying the PCIe reset specifications of the PCIe base specifications.

The specifications say that the component must enter the LTSSM detect state within 20ms of the end of the fundamental reset.

They are saying that they cannot meet this requirement because it takes 143ms to run through SBL from boot and thus cannot reach the training program within 20ms.

Could you tell us how to meet this requirement? How can they approach this issue?

Also, some additional notes they sent us:

  • They connected the PORz and PERST signal with logical OR and use it as a reset for their microcontroller as below.
  • Below indicates the time from reset to LTSSM training, and it took 145ms

Best regards,

Mari Tsunoda

  • +1
    TI__Genius 17176 points

    This is a common issue for processors that take >20ms to boot. To meet the 20ms timing, the system timing should be configured so that AM5706 has completed booting before PERST# is released. This is done by decoupling the POR and PERST# signals. PERST# can instead be used as a GPIO input to AM5706, and SW can monitor PERST# after booting to trigger the start of link training.

  • 0 in reply to B.C.
    TI__Expert 5726 points

    Hi Brad,

    The customer was able to solve their issue! Thank you!

    Best regards,

    Mari