Hi:
The following is from SPRUGL6A. My question is regarding the last sentence (Note that ----). What register is it referring to? The individual timer interrupts are cleared by writing a one to the corresponding timer bit in TIAFR. The "overall" timer interrupts are cleared by writing a one to the TINT bit in IFR0. There are not other registers that deal with interrupts from the timers. Could you please help?
Thanks a lot.
Cheers,
Mushtaq
6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h] The timer interrupt aggregation flag register (TIAFR) latches each timer (Timer 0, Timer 1, and Timer 2) interrupt signal when the timer counter expires. Using this register, the programmer can determine which timer generated the timer aggregated CPU interrupt signal (TINT). Each Timer flag in TIAFR needs to be cleared by the CPU with a write of 1. Note that the corresponding timer interrupt register must also be cleared (see the
TMS320VC5505/5504 DSP Timer/Watchdog Timer User's Guide
(Literature NumberSPRUFO2) for more information).
