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DM3730 CUS package Routing Guidelines

Hey, I have a question about the way the OMAP can/should be routed out 
on the board. My fellow students and I are working on a device for a 
school project that involves building a handheld console, and we chose 
to use the OMAP for its speed and graphics capabilities. I've been 
routing the main board out but have run into some troublesome issues 
trying to stay within the budget afforded to us. First, is the trace/ 
space widths, we want to keep them at a minimum of 5 mils, and in 
order to do so we have chosen to go with the CUS package as it allows, 
and provides a guide for, the routing to be done in said spacing. 
However, it seems the calculations of the pad sizes and via 
diameters are larger than is physically possible unless some of the 
vias are placed under the BGA pads. This isn't the suggestion, 
albeit it seems the only option at the moment. I was wondering if that 
is a bad idea to have them directly under the pads, as I fear the 
solder might not make a secure connection. Also, the chip itself has a 
ball size of 0.45 to 0.35 mm and so I made the pads for each ball 0.40 
mm. Would it be safe to go to a smaller pad size, say 0.35 mm or 0.30, 
in order to allow some of these vias to fit properly? 

Any advice in this area would be greatly appreciated. 

Thanks in advance! 

~Wylder

  • I wrote the guide, so I may be of some help to you.

    I think you've already discovered your problem.  0.4mm pad is way too big for a 0.4mm (nominal) diameter ball.  If you reference the standard for setting BGA pad sizes, IPC.org specification IPC-7351 (helpfully shown at http://s3-blogs.mentor.com/tom-hausherr/files/2011/01/table-1-land-approximation-mm-for-collapsible-solder-balls.png), you'll see that in general, pad sizes are set to about 25% of the maximum ball diameter.  If you'd like to understand why, reference http://e2e.ti.com/support/dsp/davinci_digital_media_processors/int-dm81x/f/518/p/104058/367238.aspx#367238

    Using the proper 0.3mm diameter BGA pad for this package, you can it with 18 mil diameter vias, which can use a 10 mil hole or 8 mil hole, depending on what your particular board shop prefers.  This will allow a 5 mil trace.

    Using a 4 mil trace allows 20 mil diameter vias with a 10 mil finished hole size.

     

    You can't put vias under the pads for a number of reasons, one of which is that it will suck the solder down into the hole and away from the BGA.  If there was a good way around this, for through hole via boards, it would have been done already, but unfortunately there isn't. 

    There are via-in-pad technologies, but are only offered at a much higher price point and use a micro via (laser drilled) multi-step HDI (High Density Interconnect) process. 

    The cheapest CUS routing in production is 4 mil trace/space with a 20 mil diameter via and 10 mil hole, but prototype shops sometimes prefer other sizes.  Please make sure to work with your board shop to see what they prefer before you lay out the board.  That will give you the lowest cost and most reliable board.

     

    Good luck!

  • Thanks a lot Keven, that cleared things up for me! I have one more question though about the vias. Can/should I place the vias closer than 5 mils of the pad they're connected to? I've spoken with a few board shops and some say it's a problem and others say they wouldn't know until they had the files. I can make it so there is still the 5 mil spacing there too but I was wondering if it was a bad idea or not more out of curiosity than anything else.

     

    Thanks again!

    ~Wylder

  • Generally if the board shop says they support a 5 mil trace, they usually also support a 5 mil clearance in general, so you should space things out =>5mils in all cases between all things (unless it's between power plane splits, which typically are separated by at least 10-20 mils).  If they support 4 mil traces, they usually also support 4 mil clearances.

    Sometimes they'll make an exception between features on the same net, like vias to the PCB pads they're connected to, but it's not a good idea to take advantage of this unless absolutely necessary because as you found out, not all board shops are comfortable with this.  If you get the vias too close to the pads, they will suck the solder away from the pad, which is bad.

    This package, when routed with 18 mil vias, supports a 5 mil trace and a 5 mil clearance, so you don't have to do this.

    Have fun!