AM6548: DDR Mode register Read/Write

Milan Oklobdzija32

Part Number: AM6548
Other Parts Discussed in Thread: SYSBIOS

Hello All,

I have a question regarding reading Mode Register Contents of LPDDR4 memory that we use on our custom AM6548 based board.
Idea was to read specifically MR5 register which contains Manufacturer ID information.
Thus, we could use various DDR modules (but of the same characteristics) from several manufacturers (eg. Micron, ISSI etc.) and have a different DDR controller configuration for them if needed.

My configuration is:
CCS ver: 9.2.0.00013
PDK - pdk_am65xx_1_0_7 (processor_sdk_rtos_am65xx_6_03_00_106)
SYSBIOS - 6.76.3.01

I wanted to perform read of MR5 Mode register by issuing Mode Register Read command to the LPDDR4 module.
In order to do so I used write/read to DDRCTL_MRCTRL0, DDRCTL_MRCTRL1 and DDRCTL_MRSTAT registers inside PDK's \packages\ti\board\src\cbsKeystone3\board_ddr.c file.
Specifically, I entered the following lines after call to DDR_Controller_PHY_Config() inside Board_DDRInit(void) function:

while(HW_RD_REG32(CSL_DDRSS0_CTL_CFG_BASE + CSL_EMIF_CTLCFG_MRSTAT) & 0x01) {}
HW_WR_REG32(CSL_DDRSS0_SS_CFG_BASE + CSL_EMIF_CTLCFG_MRCTRL0,0x00000011);
boardDDRDelay();
while(HW_RD_REG32(CSL_DDRSS0_CTL_CFG_BASE + CSL_EMIF_CTLCFG_MRSTAT) & 0x01) {}
HW_WR_REG32(CSL_DDRSS0_SS_CFG_BASE + CSL_EMIF_CTLCFG_MRCTRL1,0x00000500);
boardDDRDelay();
while(HW_RD_REG32(CSL_DDRSS0_CTL_CFG_BASE + CSL_EMIF_CTLCFG_MRSTAT) & 0x01) {}
HW_WR_REG32(CSL_DDRSS0_SS_CFG_BASE + CSL_EMIF_CTLCFG_MRCTRL0,0x80000011);
boardDDRDelay();
while(HW_RD_REG32(CSL_DDRSS0_CTL_CFG_BASE + CSL_EMIF_CTLCFG_MRSTAT) & 0x01) {}
s32DdrId = HW_RD_REG32(CSL_DDRSS0_CTL_CFG_BASE + CSL_EMIF_CTLCFG_MRCTRL1) & 0xFF;

Here I first wait for previous Mode Register Read command to be completed and then configure MRCTRL0 register with command set to MRR and rank zero.

Address (0x5) is loaded in MRCTRL1 (bits [15:8]) and then I issue a Mode Register Read command and read result from MRCTRL1 register.
I also tried inserting the same lines after DDR training was successfully completed in Board_DDRInit(void).
However, I always get zero value read zero in data bits ([7:0]) from CSL_EMIF_CTLCFG_MRCTRL1 register.

Micron LPDDR4 that we are currently using is correctly configured and we performed successful memory tests and are running the code from DDR withut any problems.
Can somebody give me a hint what am I doing wrong here?

Best regards,
Milan

over 4 years ago

0 kcastille over 4 years ago

TI__Guru 54897 points

Milan,

Can you provide the part numbers for the memories you are using? If the "geometry" (rows, columns, banks, etc) is the same then it should be possible to use a single configuration that is compatible with both memories.

Regards,

Kyle

0 Milan Oklobdzija32 over 4 years ago in reply to kcastille

Intellectual 350 points

Hi Kyle,

Thanks for the reply. Alternative parts that we want to use for LPDD4 are:

ISSI IS46LQ32128A-062BLA2
Winbond W66CL2NQUAFJ

My coworker is finishing entering parameters in TI EMIF tool so I should have the configuration for those modules soon.

But is it possible to access LPDDR4 MRx registers in the way I tried?
This could help us a lot if there are some significat differences in configuration.

Best regards,
Milan

0 Milan Oklobdzija32 over 3 years ago in reply to Milan Oklobdzija32

Intellectual 350 points

Hi Kyle,

Sorry I forgot to write that our default memory module that we use now is Micron MT53E128M32D2DS-046 module.
Alternatives are listed in the message above.

Best regards,
Milan

0 kcastille over 3 years ago in reply to Milan Oklobdzija32

TI__Guru 54897 points

Milan,

It's not clear why the Mode Register read isn't working. That said, we did review your memory part numbers and it looks like the basic configuration (namely rows/banks/columns/channels) is the same for all 3 memories. It should be possible to use a configuration that is compatible with all 3 memory part numbers.

Regards,

Kyle

0 Milan Oklobdzija32 over 3 years ago in reply to kcastille

Intellectual 350 points

Hi Kyle,

Thanks on the information on this.
We will make a common DDR configuration and try it.
Currently this seems possible but I will confirm that and let you know as soon as we test.
Should we keep this thread open for that or should we close this and I make another post if we experience some problems?

Best regards,
Milan

0 kcastille over 3 years ago in reply to Milan Oklobdzija32

TI__Guru 54897 points

Milan,

We can keep it open. I can mark it as "waiting for customer" so that our moderators aren't bothered by it.

Thanks,

Kyle

0 Milan Oklobdzija32 over 3 years ago in reply to kcastille

Intellectual 350 points

Hi Kyle,

We are having big problems with board where ISSI LPDDR4 memory is used instead of Micron memory.
Here, we use ISSI IS46LQ32128A-062BLA2 instead of Micron MT53E128M32D2DS-046.
I have two boards on my side with ISSI memory and I cannot pass Write Leveling training step.
First, I tried to use modified board library/SBL for TI-RTOS but then switched to emulator initialization via gel files to avoid slow building process.
By using TI EMIF Tool 2.02 I created configuration that should be used on both Micron and ISSI memory (see attached AM65x_DRA80xM_LPDDR4_1333MTs_EMIFToolConfig_ISSI.txt)
This works on board with Micron memory but not on the board with ISSI.
Write leveling training fails with a message:

DDR not initialized with R5 connect.

Go to menu Scripts --> DDR_Initialization to initialize DDR.

====

MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000
MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040
MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked!
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked!
MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled
MCU_PULSAR_Cortex_R5_0: GEL Output:
PHY Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F
MCU_PULSAR_Cortex_R5_0: GEL Output:
Waiting for DRAM Init to complete...
MCU_PULSAR_Cortex_R5_0: GEL Output:
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output:
Waiting for write leveling to complete
MCU_PULSAR_Cortex_R5_0: GEL Output:
Write leveling done
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F
MCU_PULSAR_Cortex_R5_0: GEL Output: ****ERROR in Write Leveling****
MCU_PULSAR_Cortex_R5_0: GEL Output: checking Write Leveling status per byte...
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX0GSR0 = 0x00D334E0
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX1GSR0 = 0x00CE33E0
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX2GSR0 = 0x00D33360
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX3GSR0 = 0x00D434E0
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX4GSR0 = 0x00010000
MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211
MCU_PULSAR_Cortex_R5_0: GEL Output:

====

LPDDR4 Initialization has FAILED!!!!
DDR is configured for 666MHz operation
====

From what I can see from register output here is that there is a PLL lock for certain DATX8 but write leveling always fails.

Then I tried changing Impedance setting to TI default 60/40 Ohm but that did not work also.
After this I tried changing some timing values connected with write leveling (WLMRD = 60tck and tWLWPRE = 30tCK and also tWLO=40ns) but this also did not work.
Also, I tried using slower edge but this did not help:
Slew Rate: Addr/Ctrl/Clk Medium_Fast_Mode
Slew Rate: Data/Strobe Medium_Fast_Mode

I always get a Write leveling failure with very similar register output as above.

All of these configurations work on board with Micron memory (at least it passes the training steps without problems).

From what we can tell both Sitara and LPDDR4 memory are correctly assembled with all the passive components (power capacitors, pull-up/down resistors) on the two boards with ISSI memory that we have. Power supply voltage is also present and of correct value.

Do I have some serious mistake in EMIF Tool settings that would cause this?

Is there any interaction with LPDDR4 memory before write leveling stage?
From what I can see only DDR controller is initialized on Sitara before this step (DDR_Controller_PHY_Config(), PHY_Init(), SDRAM_Init(0x7)).

Is there a way (by setting/reading some DDR controller registers) that I can check if memory is receiving commands on CA bus since Mode Reg Read/Write is not working?

Yes also important to add is that Sitara can run the app from MSMC internal memory without a problem.

Best regards,
Milan

Fullscreen AM65x_DRA80xM_LPDDR4_1333MTs_EMIFToolConfig_ISSI.txt Download

Memory_Type LPDDR4
DDR_Memory_Frequency 666
DDR_device_width 32
DDR_Width 32
ECC_Enable No
DDR_Rank Single_Rank
Data_Rate 1333
DDR_Density 4
Number_of_Rows 14
Number_of_Columns 10
Total_number_of_banks 8
DDR_ODT_value RZQ/5
DDR_DynRtt_value disabled
DDR_ODI_value RZQ/5
AM65x_Rtt_value 48
AM65x_Ron_AC_value 48
AM65x_Ron_DQ_value 48
AM65x_AC_Slew Fast_Mode
AM65x_DQ_Slew Fast_Mode
Read_Latency_(RL) 14 NOPOP
Write_Latency_(WL) 8 NOPOP
Write_Latency_(WL) NOPOP NOPOP
tRTW NOPOP NOPOP
tRP 3 21
tRCD 4 18
tWR 6 18
tRAS 3 42
tRC 0 NOPOP
tFAW 20 40
tRRD 4 10
tWTR 8 10
tXP 5 7.5
tXPDLL 0 0
tXSR 0 NOPOP
tXSDLL NOPOP 0
tRTP 8 7.5
tCKE 4 7.5
tCKESR 0 NOPOP
tZQCS 128 0
tZQoper 512 0
tZQinit 1024 0
tRFC 0 350
tRAS(max) 0 NOPOP
tREFI 0 3904
tMRD 10 14
tMOD 24 15
tWLMRD 40 0
tDLLK 768 0
tODTon_tODToff(max) NOPOP 3.5
tXPR 5 NOPOP
tWLO(max) 0 20
tCCD 8 0
tCPDED 4 0
tCKSRX 5 10
tCKSRE 5 10
tRFC2 0 260
tRFC4 0 160
tCAL 5 0
tWPRE 1.8 0
tRPRE 1.8 0
tCCD_S 4 0
tRRD_S 4 3.3
tWTR_S 2 2.5
tMPX_LH 0 12
tMPX_S 0 0.255
tXS_FAST 0 NOPOP
tXS_ABORT 0 NOPOP
tXMP NOPOP NOPOP
tXMPDLL NOPOP NOPOP
tCKMPE NOPOP NOPOP
tMRD_PDA 16 10
PL 0 NOPOP
AL 0 NOPOP
tPAR_ALERT_PW(max) 144 0
tCRC_ALERT_PW(max) 10 0
PW_RESET 0 100
tDQSCKmin 0 1.5
tDQSCKmax 0 3.5
tWLWPRE 20 0
tZQLAT 8 30
tVRCG_ENABLE 0 200
tVRCG_DISABLE 0 100
tCMDCKE 3 1.75
tODTUP 0 20
tCKELPD 0 0
tRPST 0.4 0
tMRWCKEL 10 14
tMRW 10 10
tCKCKEH 3 1.75
tCKELCK 5 5
tSR 3 15
tESCKE 3 1.75
tODTLon 6 0
tODTLoff 22 0
tCCDMW 32 0
tPPD 4 0
tZQCAL 0 1000
tZQReset 3 50
tODTon(min) 0 1.5
BL NOPOP NOPOP
31 NA
30 NA
29 NA
28 row15
27 row14
26 row13
25 row12
24 row11
23 row10
22 row9
21 row8
20 row7
19 row6
18 row5
17 row4
16 row3
15 row2
14 row1
13 row0
12 bank2
11 bank1
10 bank0
9 col9
8 col8
7 col7
6 col6
5 col5
4 col4
3 col3
2 col2

0 Milan Oklobdzija32 over 3 years ago in reply to kcastille

Intellectual 350 points

Hello Kyle,

I made a tests with ISSI memory on a lower clock settings of 533 and 600 MHz.
For this, I had to modify \packages\ti\drv\sciclient\examples\sciclient_ccs_init\sciclient_ccs_init_main.c to set the PLL3 clock to 266/300 MHz.
Then I tried several configurations in TI EMIF tool for ISSI memory:

533Mhz

AM65x_DRA80xM_EMIF_Tool_2.02_ISSI_od_600.xlsm - ISSI original settings converted for 533MHz clock
Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_533.xlsm - Micron original settings converted for 533MHz clock

600Mhz

AM65x_DRA80xM_EMIF_Tool_2.02_ISSI_od_600.xlsm - ISSI original settings converted for 600Mhz clock
Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_600.xlsm - Micron original settings converted for 600Mhz clock

In both cases ISSI fails on write leveling as can be seen in ISSI_Micron_test.txt.
Here I had to retain settings for registers DDRSS_DDRCTL_INIT4 and DDRSS_DDRPHY_MR3 as these are not correctly initialized in EMIF Tool for 533/600MHz frequency

I also tried Micron memory with settings:

533Mhz

Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_533.xlsm - Micron original settings converted for 533MHz clock

600Mhz

Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_600.xlsm - Micron original settings converted for 600Mhz clock

And in both cases training is successfully completed for Micron Memory.

You can find GEL file output of DDR init also in ISSI_Micron_test.txt for each test.

Best regards,
Milan

Fullscreen ISSI_Micron_test.txt Download

ISSI initialization 533MHz
-----------------------------
AM65x_DRA80xM_EMIF_Tool_2.02_ISSI_od_533.xlsm
But with:
		Write_MMR(	DDRSS_DDRCTL_INIT4	,	0x00100000	); 	/* SDRAM Initialization Register 4 */ 
		Write_MMR(	DDRSS_DDRPHY_MR3	,	0x00000029	); 	/* DDR Mode Register */ 

DDR not initialized with R5 connect.

Go to menu Scripts --> DDR_Initialization to initialize DDR.

====

MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000
MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040
MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked!
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked!
MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
PHY Init complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for write leveling to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write leveling done 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F
MCU_PULSAR_Cortex_R5_0: GEL Output: ****ERROR in Write Leveling****
MCU_PULSAR_Cortex_R5_0: GEL Output: checking Write Leveling status per byte...
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX0GSR0 = 0x010941E0
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX1GSR0 = 0x010641E0
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX2GSR0 = 0x01074160
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX3GSR0 = 0x010E42E0
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX4GSR0 = 0x00010000
MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211
MCU_PULSAR_Cortex_R5_0: GEL Output: 

====

LPDDR4 Initialization has FAILED!!!!
DDR is configured for 532MHz operation
====

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F


ISSI initialization 533MHz
-----------------------------
Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_533.xlsm
But with:
		Write_MMR(	DDRSS_DDRCTL_INIT4	,	0x00100000	); 	/* SDRAM Initialization Register 4 */ 
		Write_MMR(	DDRSS_DDRPHY_MR3	,	0x00000029	); 	/* DDR Mode Register */ 

DDR not initialized with R5 connect.

Go to menu Scripts --> DDR_Initialization to initialize DDR.

====

MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000
MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040
MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked!
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked!
MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
PHY Init complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for write leveling to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write leveling done 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F
MCU_PULSAR_Cortex_R5_0: GEL Output: ****ERROR in Write Leveling****
MCU_PULSAR_Cortex_R5_0: GEL Output: checking Write Leveling status per byte...
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX0GSR0 = 0x010B41E0
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX1GSR0 = 0x010641E0
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX2GSR0 = 0x01074160
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX3GSR0 = 0x010E42E0
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX4GSR0 = 0x00010000
MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211
MCU_PULSAR_Cortex_R5_0: GEL Output: 

====

LPDDR4 Initialization has FAILED!!!!
DDR is configured for 532MHz operation
====

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F

Micron initialization 533MHz
-----------------------------
Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_533.xlsm
But with:
		Write_MMR(	DDRSS_DDRCTL_INIT4	,	0x00100000	); 	/* SDRAM Initialization Register 4 */ 
		Write_MMR(	DDRSS_DDRPHY_MR3	,	0x00000029	); 	/* DDR Mode Register */ 

DDR not initialized with R5 connect.

Go to menu Scripts --> DDR_Initialization to initialize DDR.

====

MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000
MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040
MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked!
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked!
MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
PHY Init complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for write leveling to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write leveling done 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000003F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write Leveling completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Read DQS training to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read DQS training done 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000007F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read DQS training completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: --->>> Starting the DQS2DQ Training Process <<<---
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DQS2DQ Training done
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000807F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DQS2DQ completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Write leveling adjustment to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write leveling adjustment done 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800080FF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write Leveling Adjustment completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Read deskew to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read deskew complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800081FF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read Deskew completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Write deskew to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write deskew complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800083FF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write Deskew completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Read Eye training to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read Eye training complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800087FF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read Eye Training completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Write Eye training to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write Eye training complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80008FFF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write Eye Training completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for VREF training to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
VREF training complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000CFFF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
VREF Training completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211
MCU_PULSAR_Cortex_R5_0: GEL Output: 

====
LPDDR4 Initialization has PASSED!!!!
DDR is configured for 532MHz operation
====


ISSI initialization 600MHz
-----------------------------
AM65x_DRA80xM_EMIF_Tool_2.02_ISSI_od_600.xlsm
But with:
		Write_MMR(	DDRSS_DDRCTL_INIT4	,	0x00100000	); 	/* SDRAM Initialization Register 4 */ 
		Write_MMR(	DDRSS_DDRPHY_MR3	,	0x00000029	); 	/* DDR Mode Register */ 

DDR not initialized with R5 connect.

Go to menu Scripts --> DDR_Initialization to initialize DDR.

====

MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000
MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040
MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked!
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked!
MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
PHY Init complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for write leveling to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write leveling done 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F
MCU_PULSAR_Cortex_R5_0: GEL Output: ****ERROR in Write Leveling****
MCU_PULSAR_Cortex_R5_0: GEL Output: checking Write Leveling status per byte...
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX0GSR0 = 0x00ED3A60
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX1GSR0 = 0x00EA3A60
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX2GSR0 = 0x00ED39E0
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX3GSR0 = 0x00F03B60
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX4GSR0 = 0x00010000
MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211
MCU_PULSAR_Cortex_R5_0: GEL Output: 

====

LPDDR4 Initialization has FAILED!!!!
DDR is configured for 600MHz operation
====

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F



ISSI initialization 600MHz
-----------------------------
Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_600.xlsm
But with:
		Write_MMR(	DDRSS_DDRCTL_INIT4	,	0x00100000	); 	/* SDRAM Initialization Register 4 */ 
		Write_MMR(	DDRSS_DDRPHY_MR3	,	0x00000029	); 	/* DDR Mode Register */ 
		
DDR not initialized with R5 connect.

Go to menu Scripts --> DDR_Initialization to initialize DDR.

====

MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000
MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040
MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked!
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked!
MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
PHY Init complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for write leveling to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write leveling done 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F
MCU_PULSAR_Cortex_R5_0: GEL Output: ****ERROR in Write Leveling****
MCU_PULSAR_Cortex_R5_0: GEL Output: checking Write Leveling status per byte...
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX0GSR0 = 0x00EB3A60
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX1GSR0 = 0x00E83A60
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX2GSR0 = 0x00ED39E0
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX3GSR0 = 0x00F03B60
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DDRSS_DDRPHY_DX4GSR0 = 0x00010000
MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211
MCU_PULSAR_Cortex_R5_0: GEL Output: 

====

LPDDR4 Initialization has FAILED!!!!
DDR is configured for 600MHz operation
====

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F




Micron initialization 600MHz
-----------------------------
Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_600.xlsm
But with:
		Write_MMR(	DDRSS_DDRCTL_INIT4	,	0x00100000	); 	/* SDRAM Initialization Register 4 */ 
		Write_MMR(	DDRSS_DDRPHY_MR3	,	0x00000029	); 	/* DDR Mode Register */ 

DDR not initialized with R5 connect.

Go to menu Scripts --> DDR_Initialization to initialize DDR.

====

MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000
MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040
MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked!
MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked!
MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
PHY Init complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for DRAM Init to complete... 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DRAM Init complete
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for write leveling to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write leveling done 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000003F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write Leveling completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Read DQS training to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read DQS training done 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000007F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read DQS training completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: --->>> Starting the DQS2DQ Training Process <<<---
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DQS2DQ Training done
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000807F
MCU_PULSAR_Cortex_R5_0: GEL Output: 
DQS2DQ completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Write leveling adjustment to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write leveling adjustment done 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800080FF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write Leveling Adjustment completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Read deskew to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read deskew complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800081FF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read Deskew completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Write deskew to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write deskew complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800083FF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write Deskew completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Read Eye training to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read Eye training complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800087FF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Read Eye Training completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for Write Eye training to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write Eye training complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80008FFF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Write Eye Training completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
Waiting for VREF training to complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: 
VREF training complete 
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000CFFF
MCU_PULSAR_Cortex_R5_0: GEL Output: 
VREF Training completed successfully 
MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211
MCU_PULSAR_Cortex_R5_0: GEL Output: 

====
LPDDR4 Initialization has PASSED!!!!
DDR is configured for 600MHz operation
====

AM65x_DRA80xM_EMIF_Tool_2.02_ISSI_od_533.xlsm AM65x_DRA80xM_EMIF_Tool_2.02_ISSI_od_600.xlsm Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_533.xlsm Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_600.xlsm

0 Milan Oklobdzija32 over 3 years ago in reply to Milan Oklobdzija32

Intellectual 350 points

After consultation with ISSI and TI and their valuable suggestions several changes are introduced in board library for DDR PLL and DDR controller configuration.

First, PLL3 settings have to be modified to get ideal configuration for 666MHz memory clock (333MHz PLL3 clock). Settings are:
M=400, N=9, M2=3, SigmaDelta=4 (Sel_freq_dco automatically set to 2).
Other memory frequency setting are:
For 600MHz - M=720, N=9, M2=6, SigmaDelta =8 (Sel_freq_dco automatically set to 4)
For 533MHz - M=640, N=9, M2=6, SigmaDelta =7 (Sel_freq_dco automatically set to 4)

Several modifications had to be made in board library (for PDK 1.0.7) so that PLL3 registers could be set directly:

In file \packages\ti\board\src\cbsKeystone3\board_pll.c Board_call to PLLConfig(&pllcConfigs[CSL_DDR_PLL]); should be added in the end of function Board_PLLInitAll(void)
Also in file \packages\ti\board\src\am65xx_cbs\am65xx_cbs_pll.c PLL3 register appropriate values should be set in pllcConfigs[] (values given above)
File \packages\ti\board\src\cbsKeystone3\include\board_ddr_config.h reflected 666MHz memory clock settings from TI EMIF tool with one modification for MR22 (see below).

Second, in TI EMIF tool all impedances (Step1 System Details - DDR controller and memory) should reflect PCB line impedance values (in our case all impedances are 48 Ohm).
These changes are made on the basis of Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1.xlsm

Third, There was an error in Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1.xlsm for the parameter tODTon(min) (ODT turn-on/turn-off delays (minimum)).
It should be set to - 0tCK, 1.5ns instead of 6tCK, 1.5ns (this most probably caused occasional reading errors in case of Micron memory).

Fourth, in case of setting DDR MR22 register value TI EMIF tool sets register DDRSS_DDRPHY_MR22 to 0 and that sets controller ODT
value for Voh calibration which was set to disabled. That led to the incorrect calibration on memory.
For some reason Micron memory has no problem with this but it is an issue for ISSI memory. This has to be set according to value set for controller ODT.
In our case this was Rzq/5 – 48Ohm so DDRSS_DDRPHY_MR22=0x00000005.

Changes above resolved an issue with ISSI not passing training during initialization and also occasional reading errors in case of Micron memory.

Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1.xlsm

Processors

Processors forum

AM6548: DDR Mode register Read/Write