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Implementing ISA(PC/104) using PRU Subsystem

paddu
Intellectual 915 points

Hi,

 

In our application we need interfaces like CAN,LAN,PC104 etc.

Is it possible to implement both CAN interface and ISA(PC/104) bus interface on Sitara's PRU Subsystem?

 

Best Regards.

Paddu.

  • 0
    TI__Genius 14545 points

    Paddu,

      CAN has been supported for some time, and there is an implementation available on one of the PRU cores. We are assessing the other protocol to see if you can implement it on the second core.

  • 0 in reply to dabuan
    Intellectual 915 points

    Hello Drew,

    Any updates?

  • 0 in reply to paddu
    TI__Genius 15910 points

    Paddu,

    The existing CAN implementation actually requires two PRU cores.  Since there are only two PRU cores, we cannot implement both CAN and PC/104. 

    Please also note that the existing CAN implementation is not a certified CAN.  Additional details can be found at http://mistralsolutions.com/pes-support/support-downloads/l13x-daughter-card-documentation-software.html.

    Regards,

    Melissa

  • 0 in reply to melissaw
    Intellectual 915 points

    Melissa,

     

    Thank you,

     

    I understood that both cannot be impkemented simultaneously.

    For time being ignoring CAN interface,

    can I assume that PC/104 could be implemented with PRUSS?


    Regards.


  • 0 in reply to paddu
    TI__Genius 15910 points

    Hi Paddu,

    I will look into this and get back with you.

    Regards,

    Melissa

  • 0 in reply to melissaw
    TI__Genius 15910 points

    Hi Paddu,

    Can you provide additional details of your requirements for this ISA/ PC 104 bus?  (ie. speed, 8 or 16-bit bus, etc.)

    Thanks,
    Melissa

  • 0 in reply to melissaw
    Intellectual 915 points

    Hello Melissa,

    Thank you.

    Below is the requirement.

    Speed: 8MHz  , 16-bit bus.

    Regards.

    paddu

  • 0 in reply to paddu
    Intellectual 915 points

    Any updates?

  • 0 in reply to paddu
    Intellectual 915 points

    Hello Melissa,

    Please let me if you have any answer about this query.

    Regards.


  • 0 in reply to paddu
    TI__Genius 15910 points

    Hi Paddu,

    Two difficulties about an ISA(PC 104) implementation on the PRU are the number of required signals/pins by the 16-bit bus and the 8MHz speed.  Below are some comments and resources to help better make this assessment.

    The PRU wiki page highlights the basic PRU features available for peripheral emulation (ie. data RAM, interrupt controller, fast I/Os). 

    The existing UART solution can be used as a model for assessing the feasibility this implementation.  The software architecture document and limitations section of the quick start guide will be useful.

    Additional, below is a list of things to consider when making this analysis:

    1. Confirm what resources are required for the emulated peripheral. 
    •    How many I/O’s, timers, etc?  Are there any pinmuxing conflicts?  Because of the extensive pinout requirements of the 16-bit ISA(PC/104) bus, it may not be possible to use the PRU's fast I/O's to support all needed I/O's (each PRU has 30 inputs and 32 outputs).  Depending on the rest of your system requirements, pinmuxing may be a challenge in allocating all the required signals for ISA(PC/104).
    •    Keep in mind the PRU’s fast I/O’s are mapped to separate input and output pins.  If a bi-directional line is required, the input and output lines would need to be connected into a single line via hardware. 
    •    Note the PRU SS does not contain a timer.  One of the GP timers or a PWM signal would need to be used. 
    •    Bit banging GPIO's uses overhead.  One alternative is using the McASP or McBSP serializers.  See the UART solution for an example of how these serializers can be used.
            2.  How will these resources be used in a basic flow or software architecture?  Any interaction required with the ARM?
    •     Refer to the UART’s software architecture documentation hosted on Mistral’s website as an example.

          3.      What interrupts would be required? 

    •   Are these resources available in the PRU INTC? 

     

    A speed of 8MHz may be a stretch using the PRU.  To help estimate an emulated peripheral’s performance capabilities, consider the following:

    1. PRU interrupts are often a limiting performance factor.
    •    Since a polling mechanism is required to detect all interrupts, make sure all processes are completed in the interval between expected interrupts.  Otherwise, interrupts will be missed-- or not detected instantaneously.  If it is not a time critical function, the interrupts can be periodically monitored.

          2.    Estimate number of PRU assembly instructions required for the main processes. 

    •   The PRU runs at half of the CPU frequency.  This can be used to then used to estimate the total time a process will take.
    •    Also consider any latencies in accessing external resources (memory, reading / writing to other peripheral’s registers).

    Regards,

    Melissa