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TDA4VM: Configure Interrupt as Pulse Source for R5F

felix_123
Expert 1251 points
Part Number: TDA4VM

Hi TI,

I want to implement an Interrupt in a FreeRTOS application (PSDK v08.00). I want to use Pulsed Interrupts, since the behaviour of HwiP_irq_handler_c in packages/ti/kernel/freertos/portable/TI_CGT/r5f/port_Hwi.c (line 125-182), cleares Pending Interrupt Bits from Pulsed Interrupts BEFORE execution of ISR and Leveled Interrupt AFTER execution of ISR. In case of Leveled Interrupts, this can lead to a situation, where the Pending Interrupt bit gets cleared, although the upcoming ISR is not yet executed. This will result in a lost interrupt.

To implement the interrupt, I am using HwiP Interface. Unfortunately, I do not see a way to tell VIM, that my Interrupt has to be a Pulsed Interrupt. However, for AM64xx Devices, I found the following Documentation of HwiP Interface: https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_00_00_21/exports/docs/api_guide_am64x/structHwiP__Params.html Here HwiP_Params consists of a data field called "isPulse", which can configure any Interrupt as Pulse or Level Interrupt.

Q1: Are there plans to add this functionality also to J721e PDK? Or is there something similar already included?

In the meantime, I found the following workaround: R5FSS_VIM_INTTYPE_j register (0x0FF8041Ch + (j * 20h)) indicates whether an interrupt is a pulse or level source. This register is also writable. So I manually write 1 to the correct bit of the corresponding register (in case of interrupt idx 256, the corresponding register would be 0x0FF8051C where I write 0x1).

Q2: I this the intended usage of this register? Or are there some side effects when manipulating this register manually?

Thanks for your help and best regards,

Felix

  • +1
    TI__Guru**** 475745 points

    Hi Felix,

    Are you using OSAL API to register interrupt? 

    I see in the osal layer, you could specify the type of interrupt in the triggerSensitivity parameter. This parameter can be set to one of (OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL, OSAL_ARM_GIC_TRIG_TYPE_LEVEL, OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL) to set the type to Level interrupt in the VIM.

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Expert 1251 points

    Hi Brijesh, 

    thanks for your reply. Yes I am using OSAL API. I was a little bit confused, since the description of triggerSensitivity states: 

        uint32_t   triggerSensitivity; /*!< Set an interrupt's trigger sensitivity for 
                                        ARM cortex-A Generic Interrupt Controller(GIC)
                                        v2.0 specific implementations as @ref OSAL_armGicTrigType_t 
                                    */

    and I thought this only works for Cortex A72 and corresponding GIC. But it also works for R5 and VIM. Thanks for your hint.

    Best regards,

    Felix