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TDA4VM: EMMC

xiangxu kong
Intellectual 276 points
Part Number: TDA4VM


Dear Experts :

  Recently, when debugging EMMC on our own hardware, I encountered a problem and wanted to consult you.The same image file can be started normally on the SD card, then burn the program in SD into EMMC, and then switch to EMMC (boot0) startup mode. When starting from EMMC, sometimes it can be started from EMMC, but it can not be started normally from EMMC most of the time (see the serial port print log, it should not be running to uboot stage). With the same method of formatting EMMC, there is no problem with EMMC on the development board and it can run normally, but there are having problems on our own hardware board The error information is as follows :


U-Boot SPL 2021.01 (Oct 14 2021 - 16:40:12 +0800)
Model: Texas Instruments K3 J721E SoC
checkboard--hhw
do_board_detect
ep->header=0xadead12c
hhw-CONFIG_EEPROM_BUS_ADDRESS=0x00
hhw-ret=0x01
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')
do_board_detect
ep->header=0xadead12c
hhw-CONFIG_EEPROM_BUS_ADDRESS=0x00
hhw-ret=0x01
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
LPDDR4_Prob--------hhw
k3_lpddr4_init: hhw
k3_ddrss_init_freq----hhw
k3_lpddr4_start-----hhw
k3_lpddr4_freq_update---hhw
ddrss->ddrss_ctrl_mmr=0x114000
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS=0x80
ddrss->ddr_fhs_cnt=0xa
k3_lpddr4_freq_update: received freq change req: req type = 1, req no. = 0
k3_lpddr4_freq_update: ddrss->ddr_freq1 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq2 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq0 = 15000000
k3_lpddr4_freq_update: ddrss->ddr_clk = 1103650356
writel(0x1):ddrss->ddrss_ctrl_mmr=0x114000
writel(0x0):ddrss->ddrss_ctrl_mmr=0x114000
k3_lpddr4_freq_update: received freq change req: req type = 0, req no. = 1
k3_lpddr4_freq_update: ddrss->ddr_freq1 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq2 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq0 = 15000000
k3_lpddr4_freq_update: ddrss->ddr_clk = 1103650356
writel(0x1):ddrss->ddrss_ctrl_mmr=0x114000
writel(0x0):ddrss->ddrss_ctrl_mmr=0x114000
k3_lpddr4_freq_update: received freq change req: req type = 1, req no. = 2
k3_lpddr4_freq_update: ddrss->ddr_freq1 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq2 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq0 = 15000000
k3_lpddr4_freq_update: ddrss->ddr_clk = 1103650356
writel(0x1):ddrss->ddrss_ctrl_mmr=0x114000
writel(0x0):ddrss->ddrss_ctrl_mmr=0x114000
k3_lpddr4_freq_update: received freq change req: req type = 0, req no. = 3
k3_lpddr4_freq_update: ddrss->ddr_freq1 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq2 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq0 = 15000000
k3_lpddr4_freq_update: ddrss->ddr_clk = 1103650356
writel(0x1):ddrss->ddrss_ctrl_mmr=0x114000
writel(0x0):ddrss->ddrss_ctrl_mmr=0x114000
k3_lpddr4_freq_update: received freq change req: req type = 1, req no. = 4
k3_lpddr4_freq_update: ddrss->ddr_freq1 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq2 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq0 = 15000000
k3_lpddr4_freq_update: ddrss->ddr_clk = 1103650356
writel(0x1):ddrss->ddrss_ctrl_mmr=0x114000
writel(0x0):ddrss->ddrss_ctrl_mmr=0x114000
k3_lpddr4_freq_update: received freq change req: req type = 2, req no. = 5
k3_lpddr4_freq_update: ddrss->ddr_freq1 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq2 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq0 = 15000000
k3_lpddr4_freq_update: ddrss->ddr_clk = 1103650356
writel(0x1):ddrss->ddrss_ctrl_mmr=0x114000
writel(0x0):ddrss->ddrss_ctrl_mmr=0x114000
k3_lpddr4_freq_update: received freq change req: req type = 1, req no. = 6
k3_lpddr4_freq_update: ddrss->ddr_freq1 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq2 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq0 = 15000000
k3_lpddr4_freq_update: ddrss->ddr_clk = 1103650356
writel(0x1):ddrss->ddrss_ctrl_mmr=0x114000
writel(0x0):ddrss->ddrss_ctrl_mmr=0x114000
k3_lpddr4_freq_update: received freq change req: req type = 2, req no. = 7
k3_lpddr4_freq_update: ddrss->ddr_freq1 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq2 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq0 = 15000000
k3_lpddr4_freq_update: ddrss->ddr_clk = 1103650356
writel(0x1):ddrss->ddrss_ctrl_mmr=0x114000
writel(0x0):ddrss->ddrss_ctrl_mmr=0x114000
k3_lpddr4_freq_update: received freq change req: req type = 1, req no. = 8
k3_lpddr4_freq_update: ddrss->ddr_freq1 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq2 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq0 = 15000000
k3_lpddr4_freq_update: ddrss->ddr_clk = 1103650356
writel(0x1):ddrss->ddrss_ctrl_mmr=0x114000
writel(0x0):ddrss->ddrss_ctrl_mmr=0x114000
k3_lpddr4_freq_update: received freq change req: req type = 2, req no. = 9
k3_lpddr4_freq_update: ddrss->ddr_freq1 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq2 = 450000000
k3_lpddr4_freq_update: ddrss->ddr_freq0 = 15000000
k3_lpddr4_freq_update: ddrss->ddr_clk = 1103650356
writel(0x1):ddrss->ddrss_ctrl_mmr=0x114000
writel(0x0):ddrss->ddrss_ctrl_mmr=0x114000
spl_board_init--HHW
boot_from_devices------hhw
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
** Partition 1 not valid on device 0 **
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image tispl.bin, err - -1
spl: no partition table found
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

We use the following method to burn the image file from SD card to EMMC:

The boot method of 'emmc (boot0)' is adopted. The boot0 partition uses the methods of 'fatload' and 'mmc write' to burn the boot file from the SD card to EMMC. The root file system uses the file system copy method (the error should not reach the uboot stage).

  • 0 in reply to Keerthy J
    Intellectual 276 points

    Hi,thank you for your reply 

      My method is the same as the method in the link you provided. I repeated it again according to the method in the link, and the result is the same. In the same way, we can successfully start from EMMC on the development board every time, but we will fail on our own hardware board. 

      Also,I have a question. On our own hardware board, although we fail to boot from emmc most of the time and report the above errors, why can we start successfully sometimes .

  • 0 in reply to xiangxu kong
    TI__Guru**** 166320 points

    Hi,

    Can you please share the eMMC part that is being used? Also the size of the eMMC part? Is it same as the part in TDA4 development board?

    - Keerthy

  • 0 in reply to Keerthy J
    Intellectual 276 points

    Hi, 

    Our EMMC model is different from the development board, with a capacity of 8G, but the development board is 16g. Recently, I found that the system can start normally from EMMC by reducing the communication rate of emmcc. The modification method is in adding attribute max-frequency = < 50000000 > to sdhci0 in u-boot-2021.01\arch\arm\dts\k3-j721e-main.dtsi file.

    u-boot-2021.01\arch\arm\dts\k3-j721e-main.dtsi

    main_sdhci0:sdhci@4f80000 {

    + max-frequency = <50000000>；

    }

    After recompiling, I burn the three files tiboot3.bin tispl.bin u-boot.img into EMCC and find that it can be started from EMMC normally without previous error reports  and booting to u-boot prompt & enter the below :

    => mmcinfo

    Device: sdhci@4f80000
    Manufacturer ID: 15
    OEM: 100
    Name: 8GUF4
    Bus Speed: 50000000  //before is 200000000
    Mode: HS200 (200MHz)
    Rd Block Len: 512
    MMC version 5.1
    High Capacity: Yes
    Capacity: 7.3 GiB
    Bus Width: 8-bit
    Erase Group Size: 512 KiB
    HC WP Group Size: 8 MiB
    User Capacity: 7.3 GiB WRREL
    Boot Capacity: 31.9 MiB ENH
    RPMB Capacity: 4 MiB ENH
    Boot area 0 is not write protected
    Boot area 1 is not write protected

    So I have two questions to confirm with you :

    1).I want to know whether my method of reducing the frequency is correct, because I also see that other people have modified it from this forum 

    2).In this way, after reducing the EMMC frequency, the system can start normally from the EMMC. In the future, we should analyze the problem from which direction to make the EMMC work normally at the normal frequency 

  • 0 in reply to Keerthy J
    Intellectual 276 points

    the emmc part is samsung KLM8G1GEUF,  8GB,  the TDA4-EVM is micro brand. MTFC16GAPALBH-AAT

  • +1 in reply to Keerthy J
    Intellectual 276 points

    Hi,Keerthy

    Thanks for your help , confirmed by our hardware engineer, the EMMC startup frequency we use only supports 52M. After reducing the EMMC startup frequency, the system can start from EMMC normally.