TDA4VM: Question about ti-img-encode-decode

Hi,

Please ignore the below error. It is harmless.

[MCU2_0]   5599.276205 s: TIMEOUT: topazdd_wait_on_sync timed out waiting for writeback 0x05a80000.

Did you change anything in the memory map? or are you using default released memory map? 

The codec requires additional memory on the core on which it is running, so can you please keep the memory map same on this core?

Regards,

Brijesh

HI Brijesh,

     Thanks for your reply. The part I changed in gen_linker_mem_map.py has been marked in the above picture.

in  gen_linker_mem_map.py

#
# DDR, MSMC base and size
#

ddr_mem_addr = 0xa0000000;
ddr_mem_size = 1*GB + 448*MB; # Last 64MB is used by Linux
ddr_buf_mem_size = 512*MB;                                      --------------------------------------------->   change to 304*MB;
msmc_mem_addr = 0x70000000;

# Note, C6x_2 IPC region is just before C6x_1 resource table to allow to set MAR bit for C6x_2 IPC region to non-cached
c66x_2_ddr_ipc_addr = mcu3_1_ddr_addr + mcu3_1_ddr_size;
c66x_1_ddr_resource_table_addr = c66x_2_ddr_ipc_addr + linux_ddr_ipc_size;
c66x_1_ddr_boot_addr = c66x_1_ddr_resource_table_addr + 1*MB;
c66x_1_ddr_boot_size = 1*KB;
c66x_1_ddr_addr = c66x_1_ddr_boot_addr + c66x_1_ddr_boot_size;
c66x_1_ddr_size = 16*MB - (c66x_1_ddr_addr-c66x_2_ddr_ipc_addr);   ---------------------->  change to 26*MB;

# Note, C6x_1 IPC region is just before C6x_2 resource table to allow to set MAR bit for C6x_1 IPC region to non-cached
c66x_1_ddr_ipc_addr = c66x_1_ddr_addr + c66x_1_ddr_size;
c66x_2_ddr_resource_table_addr = c66x_1_ddr_ipc_addr + linux_ddr_ipc_size;
c66x_2_ddr_boot_addr = c66x_2_ddr_resource_table_addr + 1*MB;
c66x_2_ddr_boot_size = 1*KB;
c66x_2_ddr_addr = c66x_2_ddr_boot_addr + c66x_2_ddr_boot_size;
c66x_2_ddr_size = 16*MB - (c66x_2_ddr_addr-c66x_1_ddr_ipc_addr); -------------------------> change to 26*MB;

c7x_1_ddr_ipc_addr = c66x_2_ddr_addr + c66x_2_ddr_size;
c7x_1_ddr_resource_table_addr = c7x_1_ddr_ipc_addr + linux_ddr_ipc_size;
c7x_1_ddr_boot_addr = c7x_1_ddr_resource_table_addr + 1*MB;
c7x_1_ddr_boot_size = 1*KB;
c7x_1_ddr_vecs_addr = c7x_1_ddr_resource_table_addr + 3*MB;
c7x_1_ddr_vecs_size = 16*KB;
c7x_1_ddr_secure_vecs_addr = c7x_1_ddr_resource_table_addr + 5*MB;
c7x_1_ddr_secure_vecs_size = 16*KB;
c7x_1_ddr_addr = c7x_1_ddr_secure_vecs_addr + c7x_1_ddr_secure_vecs_size;
c7x_1_ddr_size = 16*MB - (c7x_1_ddr_addr-c7x_1_ddr_ipc_addr);    --------------------------->  change to 24*MB;

mcu1_0_ddr_local_heap_addr = mcu2_0_ddr_non_cache_addr + mcu2_0_ddr_non_cache_size;
mcu1_0_ddr_local_heap_size = 4*MB;      ---------------------------------------------------------------> change to 16*MB;
mcu1_1_ddr_local_heap_addr = mcu1_0_ddr_local_heap_addr + mcu1_0_ddr_local_heap_size;
mcu1_1_ddr_local_heap_size = 4*MB;      ---------------------------------------------------------------> change to 16*MB;
mcu2_0_ddr_local_heap_addr = mcu1_1_ddr_local_heap_addr + mcu1_1_ddr_local_heap_size;
mcu2_0_ddr_local_heap_size = 16*MB;   
mcu2_1_ddr_local_heap_addr = mcu2_0_ddr_local_heap_addr + mcu2_0_ddr_local_heap_size;
mcu2_1_ddr_local_heap_size = 4*MB;      ---------------------------------------------------------------> change to 64*MB;
mcu3_0_ddr_local_heap_addr = mcu2_1_ddr_local_heap_addr + mcu2_1_ddr_local_heap_size;
mcu3_0_ddr_local_heap_size = 2*MB;      ---------------------------------------------------------------> change to 64*MB;
mcu3_1_ddr_local_heap_addr = mcu3_0_ddr_local_heap_addr + mcu3_0_ddr_local_heap_size;
mcu3_1_ddr_local_heap_size = 2*MB;      ---------------------------------------------------------------> change to 64*MB;

Then I  run the  gen_linker_mem_map.py. The released memory map has been changed.

      And question is that how can I keep the memory map same on this core?

      I didn't find a place to configure the codec memory map,  please help me find it ? 

 Best regards!

Hi,

Could you search in the memory map? There is a local heap on mcu2_1 (or non-cached scratch memory), which is set to higher size for codec?

Also if you revert these changes, does the codec work fine? Just want to see if the issue is due to memory map changes?

Regards,

Brijesh

HI Brijesh,

     In addition to changing gen_linker_mem_map.py, we also changed k3-j721e-som-p0.dtsi. I will recover these two files then try codec again.

     Besides, I am sorry that I can't understand what you mean about search in the memory map and a local heap on mcu2_1 (or non-cached scratch memory) ?

     In fact, codec runs on core mcu2_0. video_codec_decoder_tirtos.lib is not dynamically connected  by vx_app_tirtos_linux_mcu2_1.out ，but  vx_app_tirtos_linux_mcu2_0.out. so did you mean we should find  a local heap on mcu2_0 (or non-cached scratch memory)?

     How can I search the memory map used for codec ? I didn't find any tips? and which file should I search? vx_app_tirtos_linux_mcu2_0.out.map？app_mem_map.h？or anything else?

     This is difficult for me. Please explain it in detail,thanks a lot!

     Best Regards!

HI Brijesh,

     I forgot to modify r5_mpu.xs. The problem is solved.

     Thanks a lot!

Best Regards!