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PROCESSOR-SDK-AM64X: Does R5F require Cache invalidation/write back

Robert Czech
Prodigy 170 points

Part Number: PROCESSOR-SDK-AM64X

Investigating the UDMA ADC Read example in the SDK, i see the code using cache write back and cache invalidation.

Is it necessary to write back / invalidate the cache also if the code runs only on a R5F core? 

  • 0
    TI__Guru 56285 points

    Hi Robert,

    If your data is in on-chip SRAM and the memory region is set to catchable in MPU setting, then you will need to write it back and invalidate, because it may be cached in L1 data cache. If the data is in the TCM, then no need to write it back and invalidate

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Expert 1265 points

    Hey Ming,

    I do not fully understand the answer, because it seems we have two answers here.

    One answer is that it i not possible if the data in SRAM is cached and the other one is that TCM-usage does not need any write back.

    So I can also set a region in SRAM to non-cached for the MPU, like we usually do when using shared memory. But this is not located in TCM.

    1. Does a non-cached region in SRAM also work like expected?

    2. Does TCM in general work without write back and invalidate? I'm asking since you can of course set TCM-regions to cacheable.

    regards,

    Felix

  • 0 in reply to Felix Heil
    TI__Guru 56285 points

    Hi Felix,

    1. For non-cached region in SRAM, no need for "write-back" or "invalidate".

    2. for TCM no need for "write-back" or "invalidate", because TCM is not cacheable.

    3. for cached region in SRAM, "write-back" or "invalidate" are needed.

    Best regards,

    Ming