AM1808 IBIS Model

john kaldunski

Other Parts Discussed in Thread: AM1808, AM1810

Our design is using a AM1808 in the ZWT package.

When using Hyperlinx to check the signal intergrity of our LPDDR interface we have found that the AM1808 IBIS model we downloaded has some problems.

For example the Vinh on the 1.8v inputs is 2.0v.

Is there a more up to date model available.

over 14 years ago

0 jc-ti over 14 years ago

TI__Mastermind 27585 points

Yes this is an error in the model, which is being update currently. For now you can manually change the Vinh value to match the datasheet.

Jeff

0 john kaldunski over 14 years ago in reply to jc-ti

Prodigy 110 points

The datasheet (Pg.68) says:

These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR or SATA interfaces.

Also, the DDR_CLKP/DDR_CLKN needs to be declared as [Diff_pin]s.

0 jc-ti over 14 years ago in reply to john kaldunski

TI__Mastermind 27585 points

Yes for the DDR2/mDDR interface it should match what is given in the JEDEC specification for VIH and VIL.

Thanks,

Jeff

0 john kaldunski over 14 years ago in reply to jc-ti

Prodigy 110 points

The AM1808/AM1810 ARM Microprocessor System Reference Guide(SPRUGM9A) DDR Slew Register (DDR_SLEW) (Pg.215) says a different receiver and a pull down is used for mDDR applications.

Is this correct? If so it is not supported by the IBIS model.

0 jc-ti over 14 years ago in reply to john kaldunski

TI__Mastermind 27585 points

Yes the System Reference Guide is correct. These modes are not currently in the IBIS model, but expect them to be included in the next revision.

Jeff

0 john kaldunski over 14 years ago in reply to jc-ti

Prodigy 110 points

Do you have an approximate date for the release of the updated IBIS model?

0 john kaldunski over 14 years ago in reply to john kaldunski

Prodigy 110 points

Bump.

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AM1808 IBIS Model