CSL_GpioBank_registersRegs

Hello,
as I am currently writing an abstraction for your GPIO-Implementation on top of the MCU+ SDK,
I am trying to understand the CSL_GpioBank_registersRegs structure.

As far as I understand the structure, this symbolizes a gpio-bank. And the specific pin can be accessed by applying the bitmask returned by GPIO_GET_BIT_MASK(pinNum).
In my naive thought process I would have imagined that a single 32Bit register for reading and writing would suffice for the bank.
But it seems that the registers for reading and writing are separated.
There is SET_DATA for setting the logic level to high, CLR_DATA for setting it to low, IN_DATA for reading, and the rest for interrupt handling.
But what is OUT_DATA?
The function GPIO_pinOutValueRead says

"This API determines the output logic level(value) on a specified
 *          GPIO pin."

My first guess wouold be that again this is separated for the case where the pin is set as output pin and the case where it is set as input pin.
So, am I correct to assume that when I write the logic level to the pin when it is set as output pin using SET_DATA or CLR_DATA, then that logic level could afterwards be verified reading from OUT_DATA?
Thank you for your time and trouble.


Best regards

Philip.