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How EBOOT is written to SPI Based flash on OMAP-L138

1258021
Genius 5120 points
Other Parts Discussed in Thread: OMAP-L138, OMAPL138

Hi,

I am trying to understand the EBOOT updation from PB for OMAP-L138 Processor

Processor: OMAP-L138

EVM: From Logic PD

WinCE BSP Ver: v01.00.02 

I understand that when we select ebootspiflash.bin from the PB General Configuration Properties the corresponding code that is executed is

WriteEBOOTToSPIFlash from the following path OMAPL138_AM18X\SRC\BOOT\EBOOT\SPIFLASH\flash.c

As CS0 is connected to M25P64, we have to select the SPI_CS0 from PINMUX5[7:4] shall be set to 1.

But, I had observed that PINMUX5 [7:4] being set to 0x8 in bsp_cfg.h

Then how the Chip select is generated for SPI based NOR Flash?

Thank You & Regards,

GSR