Hi.
I need help designing how to terminate "CORECLKP/N, DDRCLKP/N, PCIECLKP/N" inputs on TMS320C6678.
The SI52204-A01BGM, which outputs a low-power HCSL clock signal, is planned to be used as the clock source.
Clock chip manufacturers provide documentation on recommended designs for the following termination schemes:
1. Low Power HCSL to LVDS termination
2. Low Power HCSL to CML termination
So, among the above two methods, how should I design the termination method for the DSP clock inputs (CORECLKP/N, DDRCLKP/N, PCIECLKP/N)?
Or do I not need to design a termination scheme for the DSP clock input?
Please give me a response.
Best Regards
WSJ