Hi, I monitor ddr bandwidth by read read EMIF counter, but there are some problems.
The EMIF counter are correct when I access ddr from A72/C71, but when I access ddr from R5 or C66, the EMIF counter will be magnified, for example, I memset 0x9000000 addr (no-cache 20MB) to zero, but about 160M bytes were transferred, as shown in the figure below
On C71/A72, about 20M bytes were transferred
I learned from TRM that the ddr access path of A72/C71 and C66/R5F are diffent, Is this correct ?
Thanks
Alex
