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AM4372: How to use ADC0/1

user1201164
Expert 1770 points

Part Number: AM4372

Hi,

We have received some questions from our customers on how to use ADC.

1) How to use ADC0
They want to use CH1 to trigger ext_hw_trigger and CH2-8 to monitor the voltage periodically by software.
Is it possible to use the following settings to achieve this?
・Enable steps 0 to 7 using the ADC0_STEPEN Register.
ADC0_STEPCONFIG_0 Register setting value 0184300Ah (Table 11-23.)
　　[22:19]SEL_INP_SWC 0h (Channel 1)
　　[1-0]MODE 2h (HW synchronized, one-shot)
ADC0_STEPCONFIG_1 Register setting value 018C3008h (Table 11-23.)
　　[22:19]SEL_INP_SWC 1h (Channel 2)
　　[1-0]MODE 0h (SW enabled, one-shot)
Specify the STEPCONFIG registers from CH 3 to 8 in the same way, and operate them with SW enabled and one-shot in the same way as the STEPCONFIG_1 Register.

2) How to use ADC1
　I am thinking of using ADC0 and ADC1 in the same way.

3) How long does it take from the time ext_hw_trigger is set to Higth until the sequence in Figure 11-4 starts? Also, please let me know if there is a range in this time.

Best Regards,

Kouji Nishigata

  • 0
    TI__Guru** 111130 points

    Hello Nishigata-san,

    What software is the customer running on the ARM core that will be controlling the ADCs? The Linux ADC driver supports AM437x ADC0, but not AM437x ADC1. For RTOS comment, I would need to pull in another team member.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Expert 1770 points

    Hi,Nick

    Thanks for replying.
    I forgot to mention that the customer is planning to use Linux.
    However, since they are still in the R&D stage, they want to know how it works roughly, such as what kind of configuration they need to do.
    Please let me know if the operation in question is correct for the behavior they want.
    I will let them know that ADC1 is not supported by the Linux driver.

    Best Regards,

    Kouji Nishigata

  • 0 in reply to user1201164
    Expert 1770 points

    Hi, Nick
    I asked the customer to confirm that the OS they are using is µITRON-based, and the driver is also self-made.
    So, please answer the question in the form of directly manipulating the register of the device without OS.

    Best Regards,

    Kouji Nishigata

  • +1 in reply to user1201164
    TI__Guru** 111130 points

    Hello Kouji,

    Understood. Note that TI does not support custom software development on these forums, so we will not be able to assist the customer in writing or debugging their driver. I am sending your question to another team member to comment on the AM437x Technical Reference Manual (TRM) guidance on using ADC1.

    Regards,

    Nick

  • 0
    TI__Expert 3340 points

    Hi Kouji,

    To add onto what Nick has said, while you can use both ADCs this way, there are some special considerations to keep in mind for ADC1, as it was primarily designed to operate in differential mode, and as such there are some caveats about running it in single ended mode, namely that unless you have very low source impedance signals, they may be able to influence each-other's readings on adjacent channels. 

    I would like to point out the Analog Front End (AFE) section 12.3.2 (and 12.3.2.1) to better understand some of these features and limitations so that you can decide if this will fit within their requirements. 

    As for your last question this is described in section 12.3.1.2.2 - "the hardware event will be triggered after the EXT_HW_TRIGGER input signal transitions from low to high and is held high for a period greater than two cycles of ocp_clock."

    Best Regards,

    Andrei

  • 0 in reply to Andrei Aldea
    Expert 1770 points

    Hi, Andrei

    Thanks for the answer.
    Regarding your last question, I think they want to know when the uptake will start, after holding High for more than 2 clocks.
    I am assuming that the sequence starts on the rising edge of ADC_CLK after that signal has been held for more than 2 clocks, is that correct?

    Best Regards,

    Kouji Nishigata

  • +1 in reply to user1201164
    TI__Expert 3340 points

    Hi Kouji,

    Yes, that's correct. The one distinction to make for the sake of accuracy is that the "held high for more than 2 clocks" talks about the (usually faster) ocp_clk, while the rising-edge portion onwards references the adc_clk once the wakeup event is handed off to the ADC. 

    This is shown in section 11.2.2 TSC_ADC (ADC0) Clock and Reset Management of the TRM. (Page 1798). 

    So effectively your understanding is right, conversion starts on rising edge of ADC_CLK after event is triggered by hardware event held high for 2 ocp_clk cycles. 

    Best,

    Andrei