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Original question:

AM6442: The number of PRU_ICSS external events

AM6442: Main domain interrupt mapping problem

Ethan Tian
Intellectual 1872 points
Part Number: AM6442


Hi experts

I would want to ask how the IN is mapped to the OUT

Because I can see the formula in 9.3.3.1.2, the number of 54 [7:0] values converted to decimal notation is far more than 199

  • 0
    TI__Mastermind 28965 points

    The mapping for each of the MAIN_GPIOMUX_INTROUTER0_OUTP_[53:0] router outputs is controlled by a GPIOMUX_INTRTR0_MUXCNTL_n register. 

    There are 54 outputs and 54 registers (Offset = 4h + (n * 4h); where n = 0h to 35h). "n" is the register number and the output line number. 

    The ENABLE bit filed is used to select which input is mapped to the output controlled by the register. The ENBALE field is 8-bits in size therefore any of the 199 possible source can be selected. 

    let me know if this late answer is still not clear.  

    --Paul