TDA4VM: Two questions about DDR registers bit means and configs

hello, TI expert

There are two questions need you replay:

1)about DDRSS_PERF_CNT_SEL_REG register, what CNTn_SEL value 0x1c means?   I am not understand what is Counts every cycle for which the DDR Controller command queue is full.

2)how to get AXI bus outstanding config value?

Thanks!