Hi,
in http://focus.ti.com/lit/wp/spry161/spry161.pdf whitepaper I see following:
For example, Multicore Navigator is able to schedule jobs and instruct the next free DSP core to read a job
and process it without the need for external management. This simplifies the SoC’s software architecture and
improves the performance of base stations by providing the following:
• Dynamic resource/load sharing
• Offloading CPU overhead/delay related to inter-subsystem communications
• Hardware-based task prioritization
• Dynamic load balancing
• Common communication methodology for all IP blocks (software, I/O and accelerators)
The Multicore Navigator controls data flow without CPU intervention, freeing CPU cycles from moving
data and boosting on-chip communication by up to 20 million messages per second. It also enables simpler
software architectures allowing shorter development cycles and better utilization of resources.
This HW scheduler feature is not described in sprugr9b.pdf. I see just two options here:
4.3.1 Descriptor Accumulation Firmware
4.3.2 Quality of Service Firmware
Is there any documentation about HW schceduler firmware for PDSP?
http://www.ti.com/lit/sprugw4 link is broken.
And second question is
Where it is possible to find doc for interrupt controller for the TMS320TCI6618? I mean "Interrupt Controller (INTC) for KeyStone Devices User Guide SPRUGW4"
Best regards,
Ruslan
