TIDEP-01022: VDD_WAKE0 power pin connection

Michael Shklyarman

Part Number: TIDEP-01022
Other Parts Discussed in Thread: DRA821

Champs,

On the reference design the VDD_WAKE0 power pin is powered by a separate LDO that is switched by the PMIC. (VDD_WK_0V8). Why is it connected to a switched and enabled LDO?

Is it OK to leave the LDO out and connect it to the Core 0.8V supply? The power up sequence in the DRA821 DS Fig8-3 shows it coming up at T2 along with other 0.8V volt supplies including Core 0V8. The datasheet also shows it combined on table 10-1 with the Digital Low Voltage box

The design is not using any low power modes and will always start from a cold start.

thanks

Michael

over 3 years ago

0 Michael Shklyarman over 3 years ago

TI__Genius 12670 points

Same question about the LDO U32 on the reference design. Why the LDO for the VDD1_LPDDR_1V8 and not use the VDD_IO_1V8 rail to power the LPDDR4?

And why do they have the fancy FETs circuit, why didn’t a logic gate work here. From what I see, the VDD_IO_1V8 or H_DDR_RET1V1 turns it the LDO on

0 Michael Shklyarman over 3 years ago in reply to Michael Shklyarman

TI__Genius 12670 points

Guys, any feedback here? customer is pushing me. thanks

0 Michael Shklyarman over 3 years ago in reply to Michael Shklyarman

TI__Genius 12670 points

Another question regarding the switched voltage rails VDD_GPIORET_3V3 and VDD_IORET_3V3. They are enabled right away by the PMIC based on the waveform sequencing provided by PMIC team.

Since the customer is not using the FET Switched rail, can they also eliminate the switches for the VDD_GPIO_RET3V3 and VDD_IO_3V3 and just have one 3V3 V rail?

thanks,

Michael

0 Bill McCracken over 3 years ago

TI__Expert 6965 points

SoC 's VDD_WAKE0 input supply needs to be supplied from an independent power resource only if the system is supporting GPIO Retention low power mode. Per your comment of no low power modes are needed, then it should be grouped with VDD_CORE_0V8 power rail.

0 Bill McCracken over 3 years ago in reply to Michael Shklyarman

TI__Expert 6965 points

The VDD1_LPDDR_1V8 power rail and H_DDR_RET_1V1 support logic is only needed to support DDR Retention low power mode. If DDR_RET low power is not needed, then VDD_IO_1V8 can be used if there is sufficient current margin based upon your peripheral component selection & loadings.

0 Bill McCracken over 3 years ago in reply to Michael Shklyarman

TI__Expert 6965 points

Please clarify the following:

1. What do you mean by "FET Switched rail"?

2. Please include the targeted J7 SoC PN and recommended PDN-ID to be used.

0 Michael Shklyarman over 3 years ago in reply to Bill McCracken

TI__Genius 12670 points

Hi Bill,

to my understanding he is asking if he can eliminate VDD_GPIORET_3V3 and VDD_IORET_3V3 provided he doesnt use the circuitry powered by these rails in the reference design

we recommended the following PDN:

0 Michael Shklyarman over 3 years ago in reply to Bill McCracken

TI__Genius 12670 points

FET Switched power supply refers to the below snippets. We did not include this FET in our design. It may not be relevant.

In the reference design the Load switches and LDO’s are supplied from the voltage after the FET (red dash), so when the 3.3V comes up, it will power both the PMIC and the various VDD_xxx_3V3 nets.

Other than the eMMC, OSPI FLASH, and LPDDR4, we are not planning power up any other devices with the 1.8V.

Will the VOUT_LD01 of the PMIC be able to supply it? Maybe I will keep the LDO in.

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TIDEP-01022: VDD_WAKE0 power pin connection