mDDR Low Power Mode

Stefan Koehler

Intellectual 525 points

Hi,

I'm a bit confused regarding the DDR controller registers.

sprugj4b p.49 :

LPMODEN = 1 -> Low Power Mode Enable
LPMODEN = 0 -> Low Power Mode Disable

the defines in the CSLR (cslr_ddr2_mddr.h) are:

#define CSL_DDR2_MDDR_SDRCR_LPMODEN_LPMODE (0x00000000u)
#define CSL_DDR2_MDDR_SDRCR_LPMODEN_NO_LPMODE (0x00000001u)

Now my questions:

1) Which one is correct?
3) Is it correct, that the SDRAM refreshs/holds data while in low power mode, but can not be read from or written to?
2) Why do I have to set the bit (enable or disable?) the low power mode to do a SyncReset?

Thanks,
Stefan

over 14 years ago

0 jc-ti over 14 years ago

TI__Mastermind 27585 points

1) Follow the user guide description, 0-Disable 1-Enabled. We will update the CSLR to match this.

2) Section 2.8 of the guide will explain the behavior when you read or write during self refresh mode. Basically the chip will exit self refresh mode when the memory is accessed.

3) If the controller is reset when the SDRAM is not in self refresh mode, the contents of the memory may become corrupted.

Jeff

0 Stefan Koehler over 14 years ago in reply to jc-ti

Intellectual 525 points

Thanks for the information. I will do so.

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mDDR Low Power Mode