TDA4VM: SPI DMA does not work(QNX+RTOS, SDK8.0)

Sun Jianqiang

Part Number: TDA4VM

Hi Experts,

We have ported spi driver(psdkqa/pdk/packages/ti/drv/spi) to QNX/A72, all the baseAddr's are changed from uint32_t to uintptr_t and the baseAddr was mapped by calling mmap_device_memory. We also ported main_mcspi_slave_mode.c to QNX/A72, and finally the MCSPI0 master polling mode works well. But the DMA mode does not work. The following shows my trace process:

J7EVM@QNX:/# spi-mgr -d -t2000 -v
conf: inst 0, role master, ch 0, mode 1, mc no, poll no, cb no, dma on, duplex f, buflen 508
D:baseAddr before mapped: 2100000
D:baseAddr after mapped: 17f6df6000
D:call Udma_init
J7EVM@QNX:/# 
J7EVM@QNX:/# ps -ef|grep spi
    0     151576     135190  - 00:01 ?        00:00:00 spi-mgr -d -t2000 -v
    0     151576     135190  - 00:01 ?        00:00:00 spi-mgr -d -t2000 -v
    0     163866     135190  - 00:01 ?        00:00:00 grep spi
J7EVM@QNX:/# diagspi 
T:enter SPI_open_v1
T:enter MCSPI_open_v1
T:enter MCSPI_dmaConfig
T:leave MCSPI_dmaConfig, status=0
send: buflen 508
fe fd fc fb fa f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 ef 
ee ed ec eb ea e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 df 
de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cf 
ce cd cc cb ca c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 bf 
be bd bc bb ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 af 
ae ad ac ab aa a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 9f 
9e 9d 9c 9b 9a 99 98 97 96 95 94 93 92 91 90 8f 
8e 8d 8c 8b 8a 89 88 87 86 85 84 83 82 81 80 7f 
7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70 6f 
6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60 5f 
5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50 4f 
4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40 3f 
3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 
2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20 1f 
1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 
0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 ff 
fe fd fc fb fa f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 ef 
ee ed ec eb ea e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 df 
de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cf 
ce cd cc cb ca c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 bf 
be bd bc bb ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 af 
ae ad ac ab aa a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 9f 
9e 9d 9c 9b 9a 99 98 97 96 95 94 93 92 91 90 8f 
8e 8d 8c 8b 8a 89 88 87 86 85 84 83 82 81 80 7f 
7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70 6f 
6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60 5f 
5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50 4f 
4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40 3f 
3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 
2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20 1f 
1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 
0e 0d 0c 0b 0a 09 08 07 06 05 04 03 
D:enter spi_io_devctl
D:nbytes=508
D:enter SPI_xfer(5427044688 5427044688), xlen=508
rxbuf before xfer:
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 
T:xferv1,count=508
T:enter MCSPI_dmaTransfer
T:TXRX mode, txtriglvl=32,rxtriglvl=32
T:init:txtriglvl=32,rxtriglvl=32,txfifo=8000000,rxfifo=10000000,fifoSize=32
T:TxRx FIFOcfg=380603c9
T:setup:txtriglvl=32,rxtriglvl=32,trmode=0
T:wordCount=32, total=480 1e01f1f
T:enter MCSPI_dmaRx
T:leave MCSPI_dmaRx(0)
T:enter MCSPI_dmaTx
T:leave MCSPI_dmaTx(0)
T:blocking...
            The trace is added here, the DMA-driver does not call the callback to post transferComplete.
            psdkqa/pdk/packages/ti/drv/spi/src/v1/SPI_v1.c
            if (chObj->operMode == (uint32_t)SPI_OPER_MODE_BLOCKING)
            {
                trace_me("T:blocking...\n");
                semStatus = SPI_osalPendLock(object->transferComplete, chObj->spiParams.transferTimeout);
                trace_me("T:blocking...done(%d)\n", semStatus);
            }

T:blocking...done(-2)
T:intenable:0
T:enter MCSPI_dmaRx_cancel
T:leave MCSPI_dmaRx_cancel
T:enter MCSPI_dmaTx_cancel
            I added the MCSPI_dmaRx/Tx_cancel functions to cancel the dma transfer when the transfer get timeout.
            psdkqa/pdk/packages/ti/drv/spi/src/v1/SPI_v1.c
            if (semStatus == SemaphoreP_TIMEOUT)
            {                      
                trace_me("T:intenable:%x\n", HW_RD_REG32(hwAttrs->baseAddr + MCSPI_IRQENABLE));

            #ifdef SPI_DMA_ENABLE
                if (hwAttrs->dmaMode == (bool)true)
                    MCSPI_dmaTransfer_cancel(mcHandle);
            #endif
               ......
            }
            
            The cancel functions:

            static void MCSPI_dmaTx_cancel(MCSPI_Handle mcHandle)
            {
                SPI_Handle         handle;
                SPI_HWAttrs const *hwAttrs;
                SPI_dmaInfo       *pDmaInfo;
                Udma_ChHandle      txChHandle;
                uint64_t pDesc = 0;

                trace_me("T:enter %s\n", __func__);

                /* Get the pointer to the object and hwAttrs */
                handle   = mcHandle->handle;
                hwAttrs  = (SPI_HWAttrs const *)handle->hwAttrs;
                pDmaInfo = hwAttrs->dmaInfo;
                txChHandle = (Udma_ChHandle)(pDmaInfo->txChHandle);

                (void)Udma_ringDequeueRaw(Udma_chGetCqRingHandle(txChHandle), &pDesc);
                (void)Udma_chDisable(txChHandle, UDMA_DEFAULT_CH_DISABLE_TIMEOUT);

                trace_me("T:leave %s\n", __func__);
            }

            static void MCSPI_dmaRx_cancel(MCSPI_Handle mcHandle)
            {   
                SPI_Handle         handle;
                SPI_HWAttrs const *hwAttrs;
                SPI_dmaInfo       *pDmaInfo;
                Udma_ChHandle      rxChHandle;
                uint64_t pDesc = 0;
    
                trace_me("T:enter %s\n", __func__);
        
                /* Get the pointer to the object and hwAttrs */
                handle   = mcHandle->handle;
                hwAttrs  = (SPI_HWAttrs const *)handle->hwAttrs;
                pDmaInfo = hwAttrs->dmaInfo;
                rxChHandle = (Udma_ChHandle)(pDmaInfo->rxChHandle);
    
                (void)Udma_ringDequeueRaw(Udma_chGetCqRingHandle(rxChHandle), &pDesc);
                (void)Udma_chDisable(rxChHandle, UDMA_DEFAULT_CH_DISABLE_TIMEOUT);

                trace_me("T:leave %s\n", __func__);
            }   

            void MCSPI_dmaTransfer_cancel(MCSPI_Handle mcHandle)
            {
                SPI_Handle           handle;
                SPI_HWAttrs const   *hwAttrs;
                SPI_v1_ChnCfg const *chnCfg;
                uint32_t             chNum;

                /* Get the pointer to the object and hwAttrs */
                handle  = mcHandle->handle;
                hwAttrs = (SPI_HWAttrs const *)handle->hwAttrs;
                chNum   = mcHandle->chnNum;
                chnCfg  = &(hwAttrs->chnCfg[chNum]);

                if (chnCfg->trMode == MCSPI_TX_RX_MODE)
                {
                    (void)MCSPI_dmaRx_cancel(mcHandle);
                    (void)MCSPI_dmaTx_cancel(mcHandle);
                }
                else if (chnCfg->trMode == MCSPI_TX_ONLY_MODE)
                {
                    /* TX_ONLY Mode */
                    (void)MCSPI_dmaTx_cancel(mcHandle);
                }
                else
                {
                    /* RX_ONLY Mode */
                    (void)MCSPI_dmaRx_cancel(mcHandle);
                }
            }


[UDMA] [Error] TX ch teardown timed out!!!
T:leave MCSPI_dmaTx_cancel
rxbuf after xfer:
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 
ERROR xfer
: Connection timed out
devctl failed: errno 0,ret 5
T:enter SPI_close_v1
T:enter MCSPI_close_v1
T:enter MCSPI_dmaFreeChannel
        The following event registers will create 2 threads:
        psdkqa/pdk/packages/ti/drv/spi/soc/dma/v2/SPI_dma.c
        Udma_eventRegister(drvHandle, eventHandle, &eventPrms);
        Udma_eventRegister(drvHandle, eventHandle, &eventPrms);
        
        The MCSPI_dmaFreeChannel is called when we close our ported spi driver, and the
        Udma_eventUnRegister functions is called, but the 2 threads can't be closed as
        folling ps command shows:
J7EVM@QNX:/# ps -ef|grep spi 
    0     151576     135190  - 00:01 ?        00:00:00 spi-mgr -d -t2000 -v
    0     151576     135190  - 00:01 ?        00:00:00 spi-mgr -d -t2000 -v
    0     151576     135190  - 00:01 ?        00:00:00 spi-mgr -d -t2000 -v
    0     151576     135190  - 00:01 ?        00:00:00 spi-mgr -d -t2000 -v
    0     200730     135190  - 00:01 ?        00:00:00 grep spi
J7EVM@QNX:/#

So now, there are 2 problems as my trace shows,

(1) DMA never happens, get timeout finally

(2) The 2 threads created by Udma_eventRegister can't be destroyed by Udma_eventUnRegister

Any guide and advice would be appreciated.

Thanks,

Jianqiang

over 3 years ago

0 Sun Jianqiang over 3 years ago

Prodigy 210 points

Is there any update?

Thanks

0 Sun Jianqiang over 3 years ago

Prodigy 210 points

ringMemSize is not set before calling Udma_chOpen in MCSPI_dmaConfig.

Was the code tested before?

Regards,

Jianqiang

0 KB over 3 years ago in reply to Sun Jianqiang

TI__Guru** 105201 points

Hi Jinqiang,

The R5 based SPI driver has been tested by TI on the R5. TI has not ported the driver to QNX on the A72.

Lets first work through the parallel thread where the udma_memcpy_testapp is not working in setup under test, and then once that is functional, look more at the UDMA transaction in the SPI driver.

As indicated in your post, for UDMA ported from R5, the source / destination addresses must be used correctly on the A72, physical address when programming the descriptor, virtual when accessing otherwise. Similarly the descriptor memory should be a virtual address when being accessed.

Regards,

0 Sun Jianqiang over 3 years ago in reply to KB

Prodigy 210 points

Hi KB,

Thank you for your reply for both of my questions.

I added the following parameters, then it works now,

initPrms.virtToPhyFxn = &Udma_qnxVirtToPhyFxn;
initPrms.phyToVirtFxn = &Udma_qnxPhyToVirtFxn;
retVal = Udma_init(&gUdmaDrvObj, &initPrms);

I also added the "Teardown" logic to psdkqa/pdk/packages/ti/drv/spi/soc/dma/v2/SPI_dma.c, and the udma_memcpy_test can work even my malfunctioning spi driver run at first after boot.

Regards,

Jianqiang

+1 KB over 3 years ago in reply to Sun Jianqiang

TI__Guru** 105201 points

Hi Jianqiang.

Glad to hear it is working, and thank you for providing the feedback on both threads.

Regards,

Kip

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TDA4VM: SPI DMA does not work(QNX+RTOS, SDK8.0)