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66AK2G12: PCIe LTSSM: Why 66AK as EP cannot detect 66AK as RC? What should we investigate?

user3788809
Intellectual 900 points
Part Number: 66AK2G12

We would like to make 66AK communicate with another 66AK via PCIe.(our designed custom board)

According to the PCIE_DEBUG0 Register(2180 1728h), 66AK as RC can detect 66AK as EP(LTSSM = polling).

However, 66AK as EP cannot detect 66AK as RC(LTSSM = detect_act).

●Gen 1

●common clock architecture (100MHz clock is provided with both EP and RC)

●Although I changed out the contents of EP and RC, the behavior is also migrated.

(The fact remains that EP cannot detect RC.)

(1) What should we investigate? resister setting? pin setting? transmission line? S/W?

(2) When does 66AK execute receiver detection? Is there diffrence between EP and RC?

Don't hesitate let me know if there are insufficient information.


Thank you.

  • 0
    TI__Mastermind 27890 points

    Hello,

    Which OS are you using on both EP and RC?

  • 0 in reply to -DK-
    Intellectual 900 points

    Both OS are Linux of SDK ( ver 06.03.00.106 processor-sdk-LINUX-RT-K2G).

  • 0 in reply to -DK-
    Intellectual 900 points

    Thank you for your response.

    I executed following Sequence (1)~(4) of TRM for EP by using Linux OS of SDK ( ver 06.03.00.106 processor-sdk-LINUX-RT-K2G).

    11.14.4.13.2 PCIe as End Point
    11.14.4.13.2.1 Initialization Sequence
    Upon de-assertion of reset, the PCIe SS is configured as end point by chip-level setting in DEVCFG
    register, see Section 5.1, Control Module (BOOT_CFG). Before a root complex is allowed to access the
    configuration space of the end point, the following initialization sequence should be followed:
    (1). Make sure PLL reference clock is running.
    (2). Turn on the power domain and clock domain of PCIe module. See Section 5.2, Power Management,
    for mare details.
    (3). Set PCIE_DEV_TYPE to 0b0 in the device level register BOOTCFG_DEVCFG to operate the PCIe SS
    in RC mode, see Section 5.1, Control Module (BOOT_CFG).
    (4). Enable PLL using PCIE_PHY_PLL_CTRL register, see Section 11.14.4.8.1, Enabling the PLL, for
    details.
    (5). Wait until PLL is locked by sampling PLL_OK bit in the PCIE_PHY_PLL_CTRL register, see
    Section 11.14.4.8.1, Enabling the PLL, for details.

    However, 66AK as EP cannot be accomplished the Sequence of "(5) PLL is locked."

    When we use 66AK as EP, PLL is not locked.

    Reset, 100MHz reference clock and power-up Sequence is no prpblem,

    because LTSSM is accomplished  "L0 (PCIe configurstion is done!)" when we use 66AK as RC.

     

    -----question-----

    What is condition that PLL of EP is locked ?

    "Setting of PLL_ENABLE_VAL and PLL_ENABLE_OVL bits of PCIE_PHY_PLL_CTRL enables the internal PLL" is done, of course.

    Reset, 100MHz reference clock and power-up Sequence is no prpblem,

    I think this question is common question.

    --------------------

    Thank you.