AM6442: Using RTI Timer for CR5

42Bastian

Expert 1430 points

Part Number: AM6442

I wonder how to setup RTI for periodic interrupt. For example RTI8 for CR5_MAIN0_0.

I got the RTI setup correctly (borrowed from Hercules) but there seems to be no interrupt arriving at the VIM/VIC.

According to the manual, there is only one RTI interrupt at 0.

Do I have to enable the interrupt at some other place besides RTI and VIC?

Too bad, there are no RTI examples in the SDK.

Any tip?

over 4 years ago

0 Bin Liu over 4 years ago

TI__Guru**** 173891 points

Hi,

What do you mean by "CR5"?

What SDK do you refer to? Processor LInux SDK or MCU+ SDK?

0 42Bastian over 4 years ago

Expert 1430 points

CR5 - Cortex-R5 (CA53 has no VIC/VIM but a GIC)

MCU+ SDK

But it seems only watchdog interrupt is routed to the interrupt controller. So I go for one of the timers.

0 Bin Liu over 4 years ago in reply to 42Bastian

TI__Guru**** 173891 points

Hi,

Thanks for the clarification. I am not confident you meant the R5 (I only hear it is called R5 or R5F, this is the first time I heard CR5), so wanted to confirm.

I am routing your query to the team which supports MCU+ SDK.

+1 Ming Wei over 4 years ago in reply to Bin Liu

TI__Guru 56185 points

HI,

According to the AM64x TRM 12.5.2.1.2 RTI Not Supported Features "Real time interrupt functionality". It does support "Windowed Watchdog Timer (WWDT) feature" There are seven RTIs, 4 of them are for R5F cores: RTI8 - RTI11. There are four interrupts in VIC for those 4 RTIs: RTI8_INTR_WWD_0, RTI9_INTR_WWD_0, RTI10_INTR_WWD_0 and RTI11_INTR_WWD_0 respectively.

Best regards,

Ming

0 42Bastian over 4 years ago in reply to Ming Wei

Expert 1430 points

Ok, thanks. Missed this point.

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AM6442: Using RTI Timer for CR5