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Interfacing TMS320C6474L with AD7984 ADC

Fred Jaworsky
Prodigy 210 points

I'm looking for a way to interface the AD7984 with the subject EVM. The current approach is to connect a single ADC on McBSP0 and 2 ADC's daisy chained  on McBSP1.

The AD7984 is an 18bit A/D and the planned sample rate is 1Meg. Data sheet for the ADC indicates max delay following convert signal is 500ns although 400ns may be reasonable.

After review of SPRUG17A it appears that the SPI master mode might be viable using a CLKGDV = 2.

Element size for the single channel would need to be 20bits since there are only 18 (if that will work).

Daisy chain would have 36 bits that could be 3 reads of 12 bits and convert after xfer.

Given that the above would work, the next issue is how to generate a reliable conversion signal. The internal generator for the McBSP does not appear to provide a way of Raising a signal for conversion and holding it high for 500ns followed by read operation. SPI master mode would require use of another signal to control the conversion and provide a way of triggering the McBSP to write to DXR to perform the read operation. Looking at the Timer, It may be possible to use the output 50% duty cycle close to the 1Meg Rate but triggering the McBSP for the write would need an ISR with possible latencies.

Any help/advice appreciated.

Fred:-)

  • 0
    TI__Guru* 84110 points

    Fred,

    You have a lot of flexibility with the McBSP. I believe you can manage to interface to these devices using the McBSP and a DMA channel for each McBSP, then just interrupt the DSP when you have collected some reasonable number of samples, say 32 or so.

    If you use the SRG Sample Rate Generator to set your serial clock rate and also the width of the FS Frame Sync, you can make a convert signal with the width you need.

    You have flexibility in the construction of the serial data's frame structure. You can set the serial word length to a larger number like 32 and then mask off the extra bits later, or you can customize the frame using multiple phases with different word lengths in each phase.

    Unfortunately, 18-bit is not one of the word length choices, but you should be able to construct your frame phases so that you start with the first bit being the Most Significant of the bits that are collected in the capture phase and then use a pulldown resistor to take the DR data line to ground. Or you could use a weak bus-holder to keep the data at the LS bit, which would also be mathematically acceptable.

    This is not handing you a solution, but this is pointing out the tools you can use to design your own solution. And I hope it helps with your confidence that this can be done.

    Post back here with what you have done to complete your solution, and you will be read and followed by many engineers like yourself in the future.

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.