AM1705 EMIFB interface with SDRAM

Hello,

Kindly find below simulation circuit and simulation result for OMAP-L137 interfacing with IS42S16160:

  Figure below shows circuit which was simulated in Hyperlynx

Figure below shows simulation result of circuit above

As per our previous post, we see this problem of overshoot and undershoot in OMAP L137 & AM1705 CPU interface wih SDRAM.

Kindly comment on above at the earliest.

Regards,

Roma

What is the output impedance of the IS42S16160? Since that device is a much stronger driver than the AM17x, try using only one terminator on the IS42S16160 side so that the total impedance matches the line impedance. I ran a similar experiment and saw the overshoot reduced, although I am not using the same stackup that you are.

Jeff

Hi Jeff,

I could not ascertain output impedance of SDRAM, so I simulated by putting a single series resistor near SDRAM, and by changing the series resistor value.

Kindly note the Hyperlynx circuit:

Simulation with 22-ohm series

39-Ohm Series simulation

47-ohm series simulation

 PCB Stack-up

Yesterdays post showed simulation result for OMAP L137 reference design.

Today we have posted simulation result for AM1705, which will be our final implementation. However as in simulation we do not see a clean waveform, we are concerned the on what implementation will actually work.

We have posted above the simulation results by having a single series resistor value near SDRAM, each series resistor the undershoot and overshoot does exist.

Kindly confirm which implementation will guanrantee proper working interface.

Rgds,

Roma

Hi Jeff,

Undershoot observed in simulation is about 0.7V-0.9V, it is more than 20% of the tolerable limits. Is this acceptable?

Rgds,

Roma

The last screen shot shows it at <0.5V undershoot, so that one should be acceptable.

Jeff

Hi Jeff,

That waveform is for 47-ohm series termination resistor,  which is very very high value for a series termination. This resistor value will cause increase in rise time and fall time of waveform which will affect timing. Is this acceptable?

Rgds,

Roma

Adding termination always reduces transition speed.  That is the trade off you make, rise time vs overshoot.  A 47 ohm terminator is not unreasonable if the output impedance of the driver is low.  Just be sure to check strong and weak corners.

-Mike

Hello Michael,

Red waveform is EMIFB_CLK as received on SDRAM pin post routing.

Green waveform is EMIFB_CLK as driven by AM1705.

We have used series resistor of 39-ohm.

Card is 6-layer board with stack-up as given below.

Waveform below is post-routing simulations as seen on Hyperlynx. This simulation is done for IC model “typical”.

Figure above shows simulation result for routed EMIFB_CLK on a 6-layer card; however IC model is “Fast, Strong”.

We would like to know if this kind of waveform as observed post routing is Ok. Which IC modeling would best represent AM1705?

 Kindly revert back on above at the earliest.

 Thanks & Regards,

Roma Bhagat

1) Don't worry about the driver waveform, nobody sees it.

2) You should be running sims and min and max.  Typical is almost worthless because it is not a corner.

3) From the waveforms presented, you need more cowbell (up the terminator to 47 ohms).  Make sure you check min corner.  One usually has to balance the terminator to get acceptable results at min and a compromise on overshoot at max.

4) What is the topology of your clock trace, it does not look point to point.  If it is not point to point, you will not be able to terminate it perfectly.

-Mike

Hi Mike,

We have checked SI Simulation using 47-ohm series resistor for routed PCB (6 layer stack), for Fast-Strong IC driver.

Pls note, it is a point-to-point connection between CPU & SDRAM. Refer below to schematics.

We did a couple of changes and have following waveforms:

 Case1: 47 ohm series resistor ( series resistor placed near to SDRAM), 10K PU (placed on routed PCB near to SDRAM). We find following waveform; clock doubling at 2V threshold & nearer to 0.8V threshold

Case 2: 47 ohm series resistor ( series resistor placed near to CPU on routed PCB), 10K PU (placed on routed PCB near to SDRAM). We find following waveform; clock doubling at 2V threshold

Case 3: 47 ohm series resistor (series resistor placed near to SDRAM on routed PCB), 10K PU (placed on routed PCB near to SDRAM); however net is routed in inner layer 3 & top. We find following waveform; clock doubling at 2V threshold & nearer to 0.8V threshold

Case 4: 22 ohm series resistor (series resistor placed near to CPU on routed PCB), Thevenin's termination (placed near to SDRAM on routed PCB); routing on top layer. We find following waveform; clock doubling at 2V threshold & nearer to 0.8V threshold

We would like your opinion on above cases.

Pls. note all above SI simulations are post routing for a 6-layer board.

Would appreciate your feedback at the earliest.

Thanks & Regards,

Roma Bhagat

What do the signals look like at the die, instead of at the pin?  Sometimes the package induces enough delay that the receiver pin signal has a glitch, but the die does not.  You can select this option in the Hyperlynx scope.

-Mike