AM6548: DDRSS DDRPHY_PLLCR0 value

Daniel Marmier

Part Number: AM6548

Hi,

We have tried various speed grade settings in the spreadsheet, and this register always gets value 0x021c4000. The CPPC and CPIC fields are documented in the TRM, and should depend on the frequency.

why do we get the same value for different speeds?
can you please describe the FRQSEL field and its possible values?

Thanks and Best Regards,

Daniel

over 3 years ago

0 Kevin S over 3 years ago

TI__Mastermind 38860 points

Hi,

I have forwarded your question internally and will reply back when I have more information.

Thanks,

Kevin

0 Kevin S over 3 years ago in reply to Kevin S

TI__Mastermind 38860 points

Hi,

Per my colleague, my understanding is that the information in the TRM is incorrect.

CPPC should be set to 0xE for ref clock frequency between 260 and 533 MHz.
CPIC should be set to 0x2 for ref clock frequency between 260 and 533 MHz.
FREQSEL should be set to 0x2 for ref clock frequency between 260 and 400 MHz.

The spreadsheet tool hard-codes these values, limiting the data rate range between 1040 - 1600 MHz, or 520 - 800 MHz DDR clock.

Regards,
Kevin

0 Daniel Marmier over 3 years ago

Prodigy 220 points

Hi and thanks for the answer,

Could you also list the other values for FRQSEL? I would like to test with a DDR clock frequency < 520 MHz ...

Regards,

Daniel

0 Daniel Marmier over 3 years ago

Prodigy 220 points

BTW:
- CPPC value 0xE is *not* described in the TRM
- CPIC value 0x2 is documented to cover "PLL reference clock ranges from 198MHz to 235MHz"
So I am afraid I need some more help about this.

Thanks!

+1 Kevin S over 3 years ago in reply to Daniel Marmier

TI__Mastermind 38860 points

Hi Daniel,

Yes, as mentioned in the previous post, the information in the TRM for these bit fields is incorrect.

Per my understanding, the information below is the correct information:

CPPC:

0xE : 260 < REF_CLK <= 533
0xF : 166 < REF_CLK <= 260

CPIC:

0x2 : 260 < REF_CLK <= 533
0x3 : 166 < REF_CLK <= 260

FREQSEL:

0x0: 466 < REF_CLK <= 533
0x1: 400 < REF_CLK <= 466
0x2: 260 < REF_CLK <= 400
0x3: 166 < REF_CLK <= 260

Regards,
Kevin

0 Daniel Marmier over 3 years ago in reply to Kevin S

Prodigy 220 points

Hi Kevin,

Thanks for the answer. Can you please schedule these corrections/additions for the next revision of the TRM?

Best Regards,

Daniel M.

+1 Kevin S over 3 years ago in reply to Daniel Marmier

TI__Mastermind 38860 points

Hi Daniel,

I have submitted the change request.

Regards,
Kevin

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AM6548: DDRSS DDRPHY_PLLCR0 value