TDA4VM: TDA4 L3 cache

Hi,

MSMC RAM can be either configured as Cache or SRAM, this configuration is dictated by the board configuration data passed to the TIFS.

The board configuration is a part of the sysfw.itb file which you should see in the BOOT partition.

Yao Zhang said:

and the last the api is in pdk ，isn't in the kernle, so l3 cache is managed by MCU？

This API to query the MSMC (TISCI_MSG_QUERY_MSMC) can be called from any host not just MCU R5. A72 can also call it. In A72 U-Boot, we actually query the TIFS and adjust the overall size of the MSMC memory to reduce the size to remove the cacheable portion.

Management of the memory as Cache or SRAM however is with the TIFS running on M3 core.

Yao Zhang said:

it looks like l3 cache Default is off ?how can i check this with program，how can i call the api which demo i can changed like next doc

By default MSMC is configured as SRAM and used by C7x to run deep learning algorithms.

To change this please change the .msmc_cache_size field in j721e_boardcfg_data structure and rebuild the sysfw.itb as mentioned in SDK doc here.

Please note, if you configure MSMC as SRAM and there is a firmware (C7x default firmware) assuming that as SRAM, then it will crash, I suggest removing the C7x firmware from /lib/firmware or modifying its memory map in case you change the MSMC configuration.

Regards

Karan