TMS320C6678: CSNR bit in SPIDAT

Hi Nancy,

Nancy Wang said:

It seems that CS1 is configured,which contradictory with cs==0.

Let me explain this part,

/* hold cs active at end of transfer until explicitly de-asserted */
    data1_reg_val = (CSL_SPI_SPIDAT1_CSHOLD_ENABLE << CSL_SPI_SPIDAT1_CSHOLD_SHIFT) |
                    (0x02 << CSL_SPI_SPIDAT1_CSNR_SHIFT);
     if (cs == 0) {
         SPI_SPIDAT1 =   (CSL_SPI_SPIDAT1_CSHOLD_ENABLE << CSL_SPI_SPIDAT1_CSHOLD_SHIFT) |
                         (0x02 << CSL_SPI_SPIDAT1_CSNR_SHIFT); 
         // (CSL_SPI_SPIDAT1_CSHOLD_ENABLE << CSL_SPI_SPIDAT1_CSHOLD_SHIFT) = 1000 0000 
         // (0x02 << CSL_SPI_SPIDAT1_CSNR_SHIFT) = 0x2 0000
         //SO SPI_DAT1 = 0x1002 0000
        
                         
     }

According to SPI user guide, on page 39.

In "SPI_SPIDAT1" in source code,

• sets "CSHOLD" - which corresponds to(C2TDELAY and C2TDELAY) are not applied between transactions.
• CSNR is set as "0x02".

Here we need to confirm CSNR is pointing to CS0 and not CS1. For that we need C6678 Datasheet, in page 30. It has been mentioned the Chip select number for CS0 is "0x10", which confirms CSNR pointing to CS0.

Thanks,

Rajarajan