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66AK2G12: Norflash XIP issue

VinceGads
Prodigy 220 points

Part Number: 66AK2G12

Hello, 

I am using a custom board based on the K2G Keystone. On of the changes is a NORFLASH connected through GPMC and I am trying to XIP from it. 

When using the debugger I can see binary data written into the NORFLASH (see 1st extract) but  using the disassembly windows I am seeing no instructions recognized.

I am executing the same code out of the internal RAM (different start addr) and everything is fine with the code.

Can someone see what is going on here? I am very puzzled.

thank you,

Vincent 

  • 0
    TI__Guru**** 181226 points

    Hi Vincent,

    What OS do you use on your K2G platform? TI Linux or RTOS? Which version?

  • 0 in reply to Bin Liu
    Prodigy 220 points

    Hi,

    Actually this is without anything. Just bear metal code executed with the debugger.

  • 0 in reply to VinceGads
    TI__Guru**** 181226 points

    Hi,

    I am routing your query to our expert for comments.

  • 0 in reply to Bin Liu
    Prodigy 220 points

    Hello,

    thank you for forwarding the problem.
    Just wondering if I can some inputs.

    thank you,

    Vincent

  • 0 in reply to VinceGads
    TI__Guru** 116950 points

    Vincent,

    Unfortunately, we don`t any examples for GPMC XIP in our SDK for us to help provide as reference for this device. 

    Are you trying to boot from the GPMC using XIP or run to code in GPMC after booting ? What changes have you made to the linker command file to boot in XIP. What linker command file changes have you made to place the code section in GPMC. 

    Another thing that I noticed looking at the disassembly the values are 0xF018E59F at 0x30000000 and the value is 0xE59FF018 at 0x0c000000.Let me check internally if I can find any validation code that may help. I am sending you a private message to connect as I will only be able to share the validation code privately for reference.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Prodigy 220 points

    Hello Rahul,

    Thank you for your response,

    In the linker files, I forced everything to be starting at 0x3000_0000. Start of GPMC memory mapped in the processor. I can share with you. But everything looks ok in the map file, all functions have an address base on 0x3000_0000, instead of the 0xC00_0000 (default with CCS makefile for 66AK2G).

    Goal is to have the boot ROM branching to the NORFLASH. To verify that XIP from NORFLASH is possible I have code loaded using the debugger, I set up GPMC registers and try to branch there.
    Good you noticed the disassembly are inverted it seems that instruction are not recognized, guess is that they are 32bits instruction and the address/data busses are only 16bits...
    So I tried compiling the same code using thumb, it became better, the instructions could be recognized on the disassembly.

    Yet when trying to branch to 0x3000_08C8, from the code running within the debugger, to a simple function programmed in NORFLASH I ended up in exception. Offset 0x0C.
    Here are the screen shots of the execution:

    Cheers,

    Vincent