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McSPI SPI Slave mode operation - simo and miso are high impedance when chip select (CS) is not asserted?

Dean Harken
Prodigy 160 points

If McSPI 1 channel x is configured to operate as a slave device, can I expect that the data and clock input signals are switch to a high impedance state when the chip select is not active?  I.e. during the time when the master is not selecting the given slave, will the slave switch its other signals to high impedance?

  • 0
    Prodigy 100 points

    Hello Dean,

    I have not worked with McSPI 1 but with 3 and 4. However, it should be the same.

    I think the impedance state will depend on what it is set in the pad configuration registers. Table 7-7, "Pad Configuration Register Functionality" in the "OMAP35x Applications Processor, Technical Reference Manual", shows that.

    In your case, the registers would be: 0x480021C8 for mcspi1_clk and mcspi1_simo;

       0x480021CC for mcspi1_somi and mcspi1_cs0;

       0x480021D0 for mcspi1_cs1 and mcspi1_cs2.

    I hope that can help you,

    Frederico Lima

     

     

  • 0
    TI__Mastermind 28125 points

    Dean

    Yes, the SPI signals should go hi-z when CS is inactive to allow other slave devices to communicate with the SPI master.

    Figure 19-18 in the Technical Reference Manual (TRM) shows the OMAP35x as on of 4 slaves connected to a master.

      Paul