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the OMAP Camera ISP parallel interface clock

Michael Yu
Prodigy 80 points
Other Parts Discussed in Thread: OMAP3530

Hi: every one,

My project is connecting 73.636 MHz serial port camera through FPGA connected to OMAP3530. i want to use camera clock (73.636Mhz ) as OMAP 3530 camera interface input clock to. Please clear to me:

1) Will OMAP3530  synchronize with input clock?

2) What is max clock can be use as input clock to OMPA camera  interface and OMAP3530  will synchoronize with?

 

Sincerely,

 

Michael

 

 

  • 0
    TI__Genius 16690 points

    Michael Yu said:
    1) Will OMAP3530  synchronize with input clock?

    Yes, cam_d data input is sampled by cam_pclk and is synchronized with internal clock.

    Michael Yu said:
    2) What is max clock can be use as input clock to OMPA camera  interface and OMAP3530  will synchoronize with?

    Below is from the datasheet (SPRS507F). Please refer to the section 6.5.1.1 for the details of timing requirement for the parallel camera interface.

    6.5.1.1 Parallel Camera Interface Timing

    The parallel camera interface is a 12-bit interface which can be used in two modes:
    1. SYNC mode: progressive and interlaced image sensor modules for 8-, 10-, 11-, and 12-bit data. The
    pixel clock can be up to 75 MHz in 12-bit mode. The pixel clock can be up to 130 MHz in 8-bit packed
    mode.
    2. ITU mode provides an ITU-R BT 656 compatible data stream with progressive image sensor modules
    only in 8- and 10-bit configurations. The pixel clock can be up to 75 MHz.

  • 0 in reply to kshin
    Prodigy 80 points

    Hi:Kazunobu Shin

     

    thank you very much for your answer to my question.

    it is means that :  if input to omap pixel clock is 73Mhz, the OMAP3530 Parallel Camera interface will automatically sync with this input clock?

     

    Michael

  • 0 in reply to Michael Yu
    TI__Genius 16690 points

    Yes.

    However the data format of the camera data input has to be one of supported formats described in 12.2.4 Camera ISP Protocols and Data Formats in the TRM. Please also review the timing of other required signals in 6.5.1.1 Parallel Camera Interface Timing in the datasheet.

  • 0 in reply to kshin
    Prodigy 80 points

    Hi:

    thank you for  answer my questions.

    but I am still not very clear the function of the signal : cam_hs, cam_vs, cam _fld , cam_wen

    1) this is  input or out put signal

    2) how to us those signals

     

    Sinerely,

     

    Michael

  • 0 in reply to Michael Yu
    Prodigy 80 points

    one more question:

    the camera in my project sends pixel  data at first half of one row time and off the second half time. I use FPGA to receive the camera data and send to OMAP parallel interface.

    1) Please tell me detail how i should organized pixel data and with cam_vs, cam_hs,

    2) do I have to gereate v_bland, H_blank signal,?

    2) camera pixel signal comes out camera not evenly at time. OMAP parallel interface pixel need feed in every clock cycle?

     

    Sincerely,

     

    Michael

  • 0 in reply to Michael Yu
    Prodigy 220 points

    Hi,

    I would like to read the data arriving from the Camera ISP using the DMA on the DSP side.

    Did anybody try this?

    Thanks in advance,

    Roman