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OMAP-L138 LCDC DMA timing

David Meixner
Expert 4010 points

Other Parts Discussed in Thread: OMAP-L138

I have a few questions regarding the LCD controller on the OMAP-L138. This does not seem clear to me from the datasheet or LCDC user's guide.

When does the DMA start relative to the start of frame generation with respect to the external LCD control signals? I’m interested in both cases of from LCD_EN and from frame to frame when double buffering is used. i.e. with DMA0 and DMA1 mode. When does the second DMA start relative to the EOF bit set of the first when performing continuous frame updates?

I would also like to estimate the time from the last EOF0/1 interrupt bit being set in a frame to the start of DMA for the next frame. I know this depends on system composition so I’m mainly interested in LCDC synchronous timing events, enough to determine a minimum time if only the LCDC had access to the DDR.

Thanks,
David

  • 0
    TI__Expert 4010 points

    Is anyone able to respond to these questions?

  • 0 in reply to David Meixner
    TI__Genius 14405 points

    Hi David,

    Just want to be sure I am looking at the right question. I will need to check with the design experts on the actual timings. I understand you are basically asking the exact logic that starts the DMA activity.

    Some clarifications.

    First of all, are you asking about raster mode? and I am assuming you are talking about active TFT mode?

    Frame start is indicated by an edge on the LCD_VSYNC signal. This I believe is dependent on the settings of RASTER_TIMING_0/1/2 registers.

    By, LCD_EN, do you mean LCD_AC_ENB_CS? this signal is toggled when data is latched from the data pins using the pixel clock.

    by EOF, do you you mean when CPU recevies the interrupt or when the internal LCDC logic sets the EOF bit?