Hi.
I need some info on DDR3 routing for my design. (Fly-by / 64bits data (1GB,16bits DDR3 x 4 without ECC))
I couldn't find "length matching requirements" for the items below in the DDR3 design documentation (SPRABI1C).
1. CLK to DQS skew constraints
2. Routing distance constraints in between each DDR chip (Address/ Ctrl/ CMD/ CLK)
3. Maxim length constraints (Address/ Ctrl/ CMD/ CLK/ Data)
Best Regards
WSJ
