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AM6548: AM65x DDR4 Design and Layout Guidance

Mathias Unterstein
Prodigy 90 points
Part Number: AM6548

Hi,

I am referring to SPRACI2A (revised 2019) AM65x/DRA80xM DDR Board Design and Layout Guidelines.

Table 9 lists the max. length of traces and skew between different net classes...

My questions regarding the numbers in the table:

Number 11: what does TYP(ical) AT length of 75 ps mean? I would understand if there is a max. length, but what is "typical" in this scenario?

Number 12: The same as number 11. What is "typical" here? I would understand if there is a max. skew (difference in trace-length) allowed between ADDR_CTRL and CK traces but I don't get what "typical" could mean.

Does the ADDR_CTRL traces (just the ones which go to the termination-resistors) have to be length-matched? I can't imagine why. 

Does the ADDR_CTRL traces (just the ones which go to the termination-resistors) have to be longer than the CK-traces, because it says it is "typical" 14 ps. Or vice versa?

If these 14 ps would be defined as "maximum" ... then I would understand it! Then the length-difference between ADDR_CTRL and CK traces (again, just the ones which go to the termination-resistors) is allowed to be max. 14 ps which is appr. 1,78 mm. 

Could someone please explain in more detail?

Regards
Mathias

  • 0
    TI__Mastermind 38090 points

    Hi,

    There is a note that states "While this length can be increased for convenience, its length should be minimized." I would need to check internally to see if other's have better feedback, but my understanding is that the "TYP" is to provide guidance on a suggested / recommended value. In other words, there may not be a maximum value required, but it is recommended to target 75 ps (or less) for the referenced parameter. 

    I am not sure what you mean by "just the ones which go to the termination resistors". However, all address / control signals need to be length-matched within the group because the signals must satisfy the DRAM input timing requirements, and the SOC cannot delay each address / control pin individually. Thus, all of the address / control signals must have the same propagation delay on the PCB to ensure that the DRAM timing requirements can be met across all signals. 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 90 points

    Hi Kevin,

    thanks for your response.

    "..but my understanding is that the "TYP" is to provide guidance on a suggested / recommended value" 

    I think the recommended value would be zero, right ;-) ... anyways.

    So I now think the 14 ps mentioned in Number 12 of the table means the following:

    For the AT segments the MAX. skew between every trace within ADDR_CTRL and CK is 14 ps. And I assume that there is no need to delay the CK or ADDR_CTRL against each other. In other words: CK could have a  slightly larger propagation delay compared to ADDR_CTRL OR ADDR_CTRL could have a slightly larger propagation delay compared to CK, correct?!

    With "just the ones which go to the termination resistors" I meant that the values for A3 ans AS are somehow clear to me, because the table provides MAX values! 

    Thanks

    Mathias

  • 0 in reply to Mathias Unterstein
    TI__Guru 51465 points

    Items 11 and 12 are for the 'AT' portion of the net (from last load to termination resistor).  I think skew control is not as important for this portion of the net, and therefore the routing guidelines just provide a rough target (typical value) for customer to target, but not hard min/max values.  The specific timing portion of the PCB net (A1, A2, A3) do have more specific values (max) provided in the table.

  • 0 in reply to Robert Eschler
    Prodigy 90 points

    Thanks Robert!

    " I think skew control is not as important for this portion of the net"

    That's what I thought as well, but the table provided was a bit "unspecific" about that :-)

    Regards

    Mathias