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TDA4VM: why does A72 CPU frequence have two clocks ?

Veitch Kyrie
Intellectual 500 points
Part Number: TDA4VM

Hi TI,

I would like to know why this dts node has two clocks? which clock is truely using? could somebody explain it to me? thanks 

a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
assigned-clock-rates = <2000000000>, <200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
u-boot,dm-spl;
};

  • 0
    TI__Guru**** 162330 points

    Hi Veitch,

    Link: software-dl.ti.com/.../clocks.html

    So actual clock is  <&k3_clks 202 2> & frequency is 2 GHz.

    The other clock is GTC Global Time counter: &k3_clks 61 1

    Basically we are enabling the Global time counter before enabling the A72.

    So <&k3_clks 202 2> is the actual clock that is running at 2GHz for A72.

    If no other questions then please click on verify answer.

    Best Regards,
    Keerthy

  • 0 in reply to Keerthy J
    Intellectual 500 points

    Hi Keerthy,

    Is this clock <&k3_clks 202 2> for A72 cpu frequence? because I try to revise it to 1.6GHz， rebuild the uboot.img as well as reboot the system to see if the change takes effect via command "k3conf dump clock 202", but the output still shows 2GHz, could you please tell me why? is there anything else need to be revised too? thanks for your clarification.

  • 0 in reply to Veitch Kyrie
    TI__Guru**** 162330 points

    Hi Veitch,

    This is due to DM firmware overwriting the frequency to default 2GHz.

    Can you try the below diff in U-Boot directory of PSDK Linux.

    Index: u-boot-2020.01+gitAUTOINC+2781231a33-g2781231a33/arch/arm/mach-k3/j721e_init.c
===================================================================
--- u-boot-2020.01+gitAUTOINC+2781231a33-g2781231a33.orig/arch/arm/mach-k3/j721e_init.c
+++ u-boot-2020.01+gitAUTOINC+2781231a33-g2781231a33/arch/arm/mach-k3/j721e_init.c
@@ -378,6 +378,10 @@ void board_init_f(ulong dummy)
     if (ret)
         panic("DRAM init failed: %d\n", ret);
 #endif
+#ifdef CONFIG_ARM64
+       int tmp;
+       tmp = set_a72_clk_frequency(1600000000);
+#endif
 }
 
 u32 spl_boot_mode(const u32 boot_device)
@@ -573,3 +577,26 @@ err_load:
     rproc_reset(2);
 }
 #endif
+
+#ifdef CONFIG_ARM64
+int set_a72_clk_frequency(u64 freq) {
+       struct ti_sci_handle *ti_sci;
+       struct ti_sci_clk_ops *clk_ops;
+       int ret = 0;
+
+       writel(0x80000001, 0x688040);
+       printf("The value of PLL8_SS_CTRL register 0x%x\n", readl(0x688040));
+       ti_sci = get_ti_sci_handle();
+       clk_ops = &ti_sci->ops.clk_ops;
+
+       ret = clk_ops->set_freq(ti_sci, 202, 2, 100000000, freq, 2000000000);
+       if (ret) {
+               printk("failed to set the frequency %d\n", ret);
+               return ret;
+       }
+
+       printk("Successfully set the clock frequency to %lld\n", freq);
+
+    return 0;
+}
+#endif

    This should get you booting at 1.6GHz.

    Regards,
    Keerthy

  • 0 in reply to Keerthy J
    Intellectual 500 points

    Hi Keerthy, 

    thanks for quick reply , it can work now, I would like to ask one more question that  what are these parameters meaning? "ret = clk_ops->set_freq(ti_sci, 202, 2, 100000000, freq, 2000000000);"  from my understanding, 202 is the device id, 2 is clock id, freq is the device 202's clock frequece, but I am confused with the other two parameters? could you please explain it to me? thanks