TDA4VM: TDA4VM: TDA4 - About the delay time after SPI transmission is completed

Hi Chun chu1,

Ideally master/transmitter send data only after receiver/slave is ready to receive the data, otherwise, there could be losses, as, afaik, there is no way for master to know when it is ready.. Both should be ready before starting the transmission...

Regards,

Brijesh

Hi Brijesh,

In the continuous transmission process, if the master cannot know whether the slave is ready, how should the master set the delay time for each transmission?

Brijesh Jadav said:

Ideally master/transmitter send data only after receiver/slave is ready to receive the data

What is the fastest bps that can be achieved under this limit?

Regards,

Chun

Hi Chun Chu1,

But here in this case, you could use interrupt, FIFO and DMA modes, to wakeup slave and keep saving data in FIFO and buffer....

Regards,

Brijesh

Hi Brijesh,

I have tried to restart the slave receiving task when the slave receiving is interrupted. This can shorten the delay time between master transmissions, but it cannot be completely without delay.

And in my stress test, if the slave is not ready to receive tasks, the master starts to transmit. At this time, the spi slave driver may crash and cannot continue to receive. And the slave application layer cannot know that the spi slave driver has crashed. This is also a problem.

I think it is necessary to let the master know whether the slave is ready to receive tasks in order to improve transmission efficiency. Can you provide a good solution?

In addition, in our application, we need to use spi to transfer data between the mcu domain and the main domain. Is there any relevant spi transmission performance data for our reference?

Regards,

Chun

Hi Chun Chu1,

I really doubt it is possible from SPI protocol point of view. You could probably add some external way, like connecting GPIO from master to slave and notifying about the data being sent. 

Are you using interrupt mode or blocking mode? Have you enabling DMA mode? 

How many SPI frames are you trying to receive? 

I really dont think SPI slave task needs to be restarted. If you have sufficient frames to be received, then you could provide the buffer beforehand and then once they are captured, interrupt/callback can be used to notify the slave task..

Regards,

Brijesh

Hi Brijesh,

Brijesh Jadav said:

Are you using interrupt mode or blocking mode?

I use callback mode.

Brijesh Jadav said:

Have you enabling DMA mode? 

Not yet, but I am currently trying to start it.

Brijesh Jadav said:

How many SPI frames are you trying to receive?

The fifo only configures 32 bytes for TX/RX each, but we will use a 256-byte protocol, so it will be split into 8 frames for transmission.

Brijesh Jadav said:

I really dont think SPI slave task needs to be restarted.

I checked the MCSPI_xferSetup_v1() in \pdk_jacinto_07_03_00_29\packages\ti\drv\spi\src\v1\SPI_v1.c.

When the slave receives 1 frame each time and completes, it needs to call MCSPI_xferSetup_v1() again to start the next reception.

The current problem is that the slave needs to call MCSPI_xferSetup_v1() again after each frame is completed, so the master needs a delay to let the slave complete this action, or do I have a misunderstanding about the slave receiving process?

Hi Chun Chu1,

I dont think you would require to call xferset_v1 function again. Because internally, driver will check if there transfer is size is more, then from the ISR itself, it will submit the new request.

Anyway, i would suggest to enable DMA mode in this kind of time critical transfers. In this case, it would give completion interrupt only after entire 256bytes are available.. 

Regards,

Brijesh

Hi Brijesh,

Brijesh Jadav said:

I dont think you would require to call xferset_v1 function again. Because internally, driver will check if there transfer is size is more, then from the ISR itself, it will submit the new request.

Okay, I try to modify the receiving process in the ISR, and then test whether there is no need to call MCSPI_xferSetup_v1() again.

Brijesh Jadav said:

Anyway, i would suggest to enable DMA mode in this kind of time critical transfers. In this case, it would give completion interrupt only after entire 256bytes are available.. 

You make sense, thank you for your suggestion.

At present, I have encountered a issue when opening SPI dma mode by referring to the method in main_mcspi_slave_mode.c.

I start the dma mode of MCU_MCSPI1 (Slave) in MCU1_0 of the mcu domain, and it is normal.

But I start the dma mode of MCSPI4 (Slave) in MCU2_1 of the main domain, and an error occurred.

After further investigation, the feedback failed of Udma_eventRegister() in Udma_init(). How can I solve this issue?

Regards,

Chun

Hi Brijesh,

..\pdk_jacinto_07_03_00_29\packages\ti\drv\spi\example\mcspi_slavemode\src\main_mcspi_slave_mode.c

The example of mcspi in the path is to use A72 to enable the dma mode of MCSPI4 (Slave). Does it require different settings to enable the dma mode of MCSPI4 (Slave) on R5 mcu2_1?

Does NAVSS0_UDMAP0 support R5 mcu2_1 in main domain?

Regards,

Chun

Hi Chun,

mcu2_1 and A72 are both the cores available on the main domain, so we would have to main domain udma/navss for channel allocation.. 

do you have sciserver integrated in mcu1_0 application? Because udma is dependent on the sciserver running on mcu1_0.

Regards,

Brijesh

Hi Brijesh,

Brijesh Jadav said:

do you have sciserver integrated in mcu1_0 application?

Yes, I have call sciserver().

Hi Chun chu1

What changes did you do to build this example for mcu2_0/1? Because as per the below link, this example is supported on mpu1_0 and mcu1_0.. 

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/pdk_jacinto_08_00_00_37/docs/userguide/jacinto/faq/faq_binlist_jacinto.html

Regards,

Brijesh

Hi Brijesh,

I build mcu2_1 in vision apps, and porting the main_mcspi_slave_mode.c example of mpu1_0 enable spi dma mode to mcu2_1.

Regards,

Chun

Hi chun,

But the examples itself does not support mcu2_1 as a core, so how do you build this example? are you linking with the correct libraries?

The reason for asking these questions is, the other examples using udma on mcu2_1 are working fine, like udma memory copy example. So i am wondering if there is any issue in linking with the correct libraries.

Regards,

Brijesh

Hi Brijesh,

Brijesh Jadav said:

the other examples using udma on mcu2_1 are working fine, like udma memory copy example.

Thank you for your support. After I refer to the udma memory copy example, I successfully enable spi dma mode on mcu2_1.

I continued to test my use case and found that the initialization failed when the second set of spi dma mode was enabled on mcu2_1.

Regardless of whether MCSPI4 (Slave) initializes spi dma mode first, or MCSPI3 (Master) initializes spi dma mode first, the second set will be fail. The error message is as follows:

[MCU2_1]     21.120478 s: [UDMA]
[MCU2_1]     21.120530 s: [Error] RM Alloc RX Ch failed!!!
[MCU2_1]     21.120565 s: [UDMA]
[MCU2_1]     21.120580 s: [Error] Channel resource allocation failed!!

Remind again, my use case is that MCU_MCSPI2 (Master) in the MCU domain(MCU1_0) to actively send data to MCSPI4 (Slave) in the Main domain(MCU2_1), and use MCSPI3(Master) in the Main domain(MCU2_1) to actively send data to MCU_MCSPI1(Slave) in the MCU domain(MCU1_0).

Regards,

Chun

Hi Chun,

I think you are running out of the RX channels on mcu2_1. I think we have kept some minimal, one or two RX channels, on mcu2_1 in the resource manager.

Can you please try increasing number of  RX channels for mcu2_1 in the resource manager?

Regards,

Brijesh

Hi Brijesh,

In the path below, I see that the total number of UDMA RX channels is 124 (140-16). Is it this one?

..\pdk_jacinto_07_03_00_29\packages\ti\drv\sciclient\src\rm_pm_hal\rm\drivers\udmap\soc\j721e\udmap_cfg.c

Regards,

Chun

Hi Brijesh,

I adjusted the number of RX channels, and this problem cannot be solved.

udmap_cfg.h
/**
 * NAVSS0_UDMAP_0 total number of UDMAP receive channels
 */
#define UDMAP_NAVSS0_UDMAP_0_RX_CHAN_MAX_INDEX (300U)
--------------------------------------------------------------
udmap_cfg.c
static const struct udmap_ch_type rx_ch_types_NAVSS0_UDMAP_0[3] = {
	{
		.start = 0U,
		.end = 3U,
		.flow_start = 0U,
		.flow_end = 3U,
		.flow_utype = RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_UHCHAN),
		.oes_offset = UDMAP_RCHAN_OES_EVT_INDEX_OFFSET,
		.err_oes_offset = UDMAP_RCHAN_EOES_EVT_INDEX_OFFSET,
		.type = UDMAP_RX_UHCHAN,
		.utype = RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_UHCHAN),
	},
	{
		.start = 4U,
		.end = 15U,
		.flow_start = 4U,
		.flow_end = 15U,
		.flow_utype = RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_HCHAN),
		.oes_offset = UDMAP_RCHAN_OES_EVT_INDEX_OFFSET,
		.err_oes_offset = UDMAP_RCHAN_EOES_EVT_INDEX_OFFSET,
		.type = UDMAP_RX_HCHAN,
		.utype = RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_HCHAN),
	},
	{
		.start = 16U,
		.end = 299U,
		.flow_start = 16U,
		.flow_end = 299U,
		.flow_utype = RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_CHAN),
		.oes_offset = UDMAP_RCHAN_OES_EVT_INDEX_OFFSET,
		.err_oes_offset = UDMAP_RCHAN_EOES_EVT_INDEX_OFFSET,
		.type = UDMAP_RX_CHAN,
		.utype = RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_CHAN),
	},
};

Regards,

Chun

Hi Brijesh,

Brijesh Jadav said:

Can you please try increasing number of  RX channels for mcu2_1 in the resource manager?

I increased the number of RX channels when initialized UDMA, as follows:

int32_t appUdmaInit(void)
{
    int32_t         retVal = 0;
    uint32_t        udmaInstId, i;
    Udma_InitPrms   udmaInitPrms;

    appLogPrintf("UDMA: Init ... !!!\n");

    udmaInstId = UDMA_INST_ID_MAIN_0;
    UdmaInitPrms_init(udmaInstId, &udmaInitPrms);
    udmaInitPrms.rmInitPrms.startTxCh = 132; //133->132, Used for the second group of MCSPI
    udmaInitPrms.rmInitPrms.numTxCh = 6; //6->6, Used for the second group of MCSPI
    udmaInitPrms.rmInitPrms.startRxCh = 138; //139->138, Used for the second group of MCSPI
    udmaInitPrms.rmInitPrms.numRxCh = 2; //1->2, Used for the second group of MCSPI
    udmaInitPrms.printFxn = (Udma_PrintFxn)appLogPrintf;
    udmaInitPrms.skipGlobalEventReg = FALSE;
    #ifdef C71
    udmaInitPrms.osalPrms.lockMutex = appUdmaOsalMutexLock;
    udmaInitPrms.osalPrms.unlockMutex = appUdmaOsalMutexUnlock;
    udmaInitPrms.virtToPhyFxn = appUdmaVirtToPhyAddrConversion;
    #endif
    retVal = Udma_init(&gAppUdmaDrvObj, &udmaInitPrms);
    if(retVal!=0)
    {
        appLogPrintf("UDMA: ERROR: Udma_init failed !!!\n");
    }
    else
    {
        gUdmaDrvHandle = &gAppUdmaDrvObj;
    }

    for(i=0; i<APP_UDMA_ND_CHANNELS_MAX; i++)
    {
        gAppUdmaNDChHandle[i] = NULL;
    }


    appLogPrintf("UDMA: Init ... Done !!!\n");

    return (retVal);
}

The Udma_rmAllocRxCh() function was initialized successfully, but then another issue appeared:

[MCU2_1]     18.699230 s: [UDMA]
[MCU2_1]     18.699275 s: [Error] Ring config failed!!!
[MCU2_1]     18.699305 s: [UDMA]
[MCU2_1]     18.699319 s: [Error] FQ ring alloc failed!!!
[MCU2_1]     18.699348 s: [UDMA]
[MCU2_1]     18.699363 s: [Error] Channel resource allocation failed!!

Regards,

Chun

Hi Chun,

How many do you require on mcu2_1? I can make the change for you to try it out.

Regards,

Brijesh

Hi Brijesh,

Awesome! Thank you for your support.

In my use case, MCSPI4 (Slave) and MCSPI3 (Master) are started in mcu2_1, and both will use DMA mode. I will use a 256 bytes SPI protocol.

Regards,

Chun

Hi Chun,

Can you please apply attached patch on ti-processor-sdk-rtos-j721e-evm-08_00_00_12\pdk_jacinto_08_00_00_37 folder, rebuild all PDK libraries and try SPL example?

/cfs-file/__key/communityserver-discussions-components-files/791/BoardCfg_5F00_Alloc_5F00_8Channels_5F00_On_5F00_Mcu2_5F00_1.patch

Regards,

Brijesh

Hi Brijesh,

My current SDK version is 7.3.0, but let me try this patch first. Thank you.

Regards,

Chun

Hi Brijesh,
I checked the content of the patch you provided and have some questions.

What tool do you use to build the *.h content in the patch?

The development environment of our product is SDK7.3.0, which is a GP device. Do I only need patch sciclient_defaultBoardcfg_rm_hex.h and sciclient_defaultBoardcfg_rm.c? Or can you provide me with a method to build this patch for SDK7.3.0?

Regards,

Chun

Hi Chun,

I only changed sciclient_defaultBoardcfg_rm.c file and then rest all files are generated by using below commands from pdk\packages\ti\build folder.

make sciclient_boardcfg BUILD_HS=yes -sj4

make sciclient_boardcfg -sj4

Regards,

Brijesh

Hi Brijesh,

I use your modification and the method you provided to generate all other files in SDK7.3.0.

After that I executed the following commands in \vision_apps to rebuild all PDK libraries and try SPL example:

1.make sdk_clean
2.make -j8 sdk

After booting, it was found that the config of udma did not change according to sciclient_defaultBoardcfg_rm.c. The log is as follows:

[MCU2_1]      4.849868 s: UDMA: Init ... !!!
[MCU2_1]      4.850499 s: UDMA: startBlkCopyUhcCh=0
[MCU2_1]      4.850536 s: UDMA: numBlkCopyUhcCh  =0
[MCU2_1]      4.850561 s: UDMA: startTxUhcCh=0
[MCU2_1]      4.850583 s: UDMA: numTxUhcCh  =0
[MCU2_1]      4.850604 s: UDMA: startBlkCopyHcCh=14
[MCU2_1]      4.850625 s: UDMA: numBlkCopyHcCh  =2
[MCU2_1]      4.850645 s: UDMA: startTxHcCh=0
[MCU2_1]      4.850664 s: UDMA: numTxHcCh  =0
[MCU2_1]      4.850682 s: UDMA: startBlkCopyCh=48
[MCU2_1]      4.850703 s: UDMA: numBlkCopyCh  =1
[MCU2_1]      4.850721 s: UDMA: startTxCh=133
[MCU2_1]      4.850740 s: UDMA: numTxCh  =6
[MCU2_1]      4.850759 s: UDMA: startRxUhcCh=0
[MCU2_1]      4.850778 s: UDMA: numRxUhcCh  =0
[MCU2_1]      4.850796 s: UDMA: startRxHcCh=0
[MCU2_1]      4.850815 s: UDMA: numRxHcCh  =0
[MCU2_1]      4.850834 s: UDMA: startRxCh=139
[MCU2_1]      4.850852 s: UDMA: numRxCh  =1
[MCU2_1]      4.850870 s: UDMA:
[MCU2_1]      4.850884 s: UDMA: startFreeRing=486
[MCU2_1]      4.850904 s: UDMA: numFreeRing  =40
[MCU2_1]      4.850924 s: UDMA: startRingMon=28
[MCU2_1]      4.850944 s: UDMA: numRingMon  =3
[MCU2_1]      4.851641 s: UDMA: Init ... Done !!!
[MCU2_1]     24.195006 s: [UDMA]
[MCU2_1]     24.195025 s: [Error] RM Alloc RX Ch failed!!!
[MCU2_1]     24.195052 s: [UDMA]
[MCU2_1]     24.195066 s: [Error] Channel resource allocation failed!!

The same is the setting value before modification...

This is my patch

to-file.rar

Regards,

Chun

yes, it did not change, i still see number of RX channels is equal to 1.

ok, let me generate patch on SDK7.3 and share it.

Regards,

Brijesh

Could you please apply attached patch on ti-processor-sdk-rtos-j721e-evm-07_03_00_07\pdk_jacinto_07_03_00_29 folder, rebuild all PDK libraries and try it again?

/cfs-file/__key/communityserver-discussions-components-files/791/RM_5F00_Allocated_5F00_4Channels_5F00_On_5F00_MCU2_5F00_1.patch

Regards,

Brijesh

Hi Brijesh,

chun chu1 said:

The same is the setting value before modification...

I found the cause of this problem, because my mcu1_0 application is not running in the SRAM of the mcu domain (0x41c00000~41D00000), but in DDR_MCU1_0 (0xA0100400~A1000000).

The following code will prevent SCICLIENT_BOARDCFG_RM from being executed, and the board config will refer to the contents of SCICLIENT_COMMON_X509_HEADER_ADDR

\packages\ti\drv\sciclient\src\sciclient\sciclient.c
----------------------------------------------------
int32_t Sciclient_configPrmsInit(Sciclient_ConfigPrms_t *pCfgPrms)
{
    int32_t ret = CSL_PASS;

    if(NULL != pCfgPrms)
    {
#if defined(BUILD_MCU1_0) && (defined(SOC_J721E) || defined(SOC_J7200))
        Sciclient_DefaultBoardCfgInfo_t boardCfgInfo;

        /* populate the default board configuration */
        ret = Sciclient_getDefaultBoardCfgInfo(&boardCfgInfo);
        if (ret == CSL_PASS)
        {
            if (((uint64_t)boardCfgInfo.boardCfgLowPm >= SCICLIENT_ALLOWED_BOARDCFG_BASE_START) &&
                    ((uint64_t)boardCfgInfo.boardCfgLowPm < SCICLIENT_ALLOWED_BOARDCFG_BASE_END) &&
                    ((uint64_t)boardCfgInfo.boardCfgLowRm >= SCICLIENT_ALLOWED_BOARDCFG_BASE_START) &&
                    ((uint64_t)boardCfgInfo.boardCfgLowRm < SCICLIENT_ALLOWED_BOARDCFG_BASE_END))
            {
                pCfgPrms->inPmPrms.boardConfigLow = (uintptr_t)boardCfgInfo.boardCfgLowPm;
                pCfgPrms->inPmPrms.boardConfigHigh = 0U;
                pCfgPrms->inPmPrms.boardConfigSize = boardCfgInfo.boardCfgLowPmSize;
                pCfgPrms->inPmPrms.devGrp = DEVGRP_ALL;
                
                pCfgPrms->inRmPrms.boardConfigLow = (uintptr_t)boardCfgInfo.boardCfgLowRm;
                pCfgPrms->inRmPrms.boardConfigHigh = 0U;
                pCfgPrms->inRmPrms.boardConfigSize = boardCfgInfo.boardCfgLowRmSize;
                pCfgPrms->inRmPrms.devGrp = DEVGRP_ALL;
            }
            else
            {
                ret = Sciclient_boardCfgParseHeader(
                            (uint8_t *) SCICLIENT_COMMON_X509_HEADER_ADDR,
                            &pCfgPrms->inPmPrms, &pCfgPrms->inRmPrms);
            }
        }
#endif
        pCfgPrms->opModeFlag     = SCICLIENT_SERVICE_OPERATION_MODE_POLLED;
        pCfgPrms->pBoardCfgPrms  = NULL;
        pCfgPrms->isSecureMode   = 0U;
        pCfgPrms->c66xRatRegion  = 15U;
        pCfgPrms->skipLocalBoardCfgProcess = FALSE;
    }
    else
    {
        ret = CSL_EFAIL;
    }

    return ret;
}

Should I rewrite the content of SCICLIENT_COMMON_X509_HEADER_ADDR (0x41cffb00)? How to implement it?

Regards,

Chun

Hi Chun,

No, please dont change. I would suggest to move the mcu1-0 application back to SRAM of mcu domain, get first it working and then make changes in memory map to move few sections to DDR. Please keep still RM and PM sections to SRAM only.

Regards,

Brijesh

Hi Chun chu & Brijesh,

I am also trying to use MCSPI communication with MCU2_1 as master and mcu1_0 as a slave.

Currently I am referring  --> "/drv/spi/example/mcspi_slavemode" for using MCU1_0 as slave and same application for MCU2_1 as master.

We have generated MCSPI_Slave_TestApp and MCSPI_Master_TestApp, so are we supposed to follow Multicore App image generation process to verify Master-Slave interaction ?

Thanks & Regards,

Piyush

Hi,

To the people who are new to TDA4VM and who are stuck at multicore app generation,

i have tried the following link to successfully integrate these two apps -->

1. MCSPI_Slave_TestApp

2. MCSPI_Master_TestApp

To do that please follow this link -->

"https://e2e.ti.com/support/processors-group/processors/f/processors-forum/902713/compiler-tda4vm-how-to-communicate-with-external-devices-using-mcu_spi-as-slave/3344543#3344543"

Although this link points to PSDKRA version 6, but i have tried the specified steps for PSDKRA 07_03_00_07 and was successful in that.

Hope this helps in getting a better grasp of TDA4VM.

Thanks TI Team, but i still hope that i had got this link on one of my post -->

"">e2e.ti.com/.../tda4vm-issue-with-multi-core-image-application-process-linux-ti-rtos"

for which is till haven't got any reply for.

Hi Brijesh & Chun chu,

I have been directed to this thread from 

--->https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1065345/tda4vm-how-to-integrate-mcspi-master-and-slave-example-application/3942621#3942621

as I want to build the code MCU2_1 as master

1.changes in component.mk == changes in spi_component.mk

MCSPI_Master_TestApp_$(SOC)_CORELIST = mcu1_0 to MCSPI_Master_TestApp_$(SOC)_CORELIST = mcu2_1

Only this change is supposed to make for now,am I right?

Please correct me if I am wrong.

Thanks  Regards

Tanvi

Tanvi,

These changes are fine, but i dont think SPI library is getting build for mcu2_1, so as i suggested earlier also, please build all pdk libraries for all cores by using "make pdk_libs_allcores" commands from build folder.. Then you should be able to get SPL example's binary for mcu2_1. 

Regards,

Brijesh

Hi Brijesh,

Thank you for understanding and being patient with us.

as per guidelines

----->build libraries for all cores

------>changes made in component.mk

------->tried to run Master on MCU2_1..."SPI master initialised" as attached SS.

------>changes made in component.mk for MCU1_0 as slave

------->tried to run Master on MCU1_0..."SPI slave initialised" as attached SS.

they initialised smoothly when individual app is ran.

but for combined image it get stuck at

SBL Revision: 01.00.10.00 (Dec 29 2021 - 15:36:15)

TIFS ver: 21.1.1--v2021.01a (Terrific Lla

What do you mean by "SPL example's binary",how can I identify or is there other method to make it?

requesting your assistance in taking this forward.

.

Regards 

Tanvi

Tanvi,

Are you able to run these examples from CCS? If not, can you first try running them from CCS? 

If SBL is stuck, then most likely combined app image is not generated correctly.. So i would suggest first running them through CCS, get it working and then run it using SBL.

Regards,

Brijesh

We are unable to run the project on CCS as we don't have jtag debugger, we are in the process of procurring the same.

In mean time can you recommend any other way to debug SBL without jtag ?

However, we will try to work MCU1_0 as master and MCU2_1 as slave, if this works I think one of our two doubts will get cleared.

Thanks & Regards,

Tanvi

Hi Tanvi,

How do you convert the binary into single app image? Could you please share the exact steps? 

Regards,

Brijesh

Hi Brijesh,

I am referring this thread to create multicore image.

---->e2e.ti.com/.../3344543

as per this 

step 1

created binary for each master and slave

-->make -s MCSPI_(Master/slave)_TestApp BOARD=j721e_evm SOC=j721e BUILD_PROFILE=release CORE=(mcu2_1/mcu1_0) BUILD_OS_TYPE=tirtos

step 2

generated master.rprc & slave.rprc files from bin folders are copied and placed into  

/pdk_jacinto_07_03_00_29/packages/ti/boot/sbl/tools/multicoreImageGen/bin

step 3

in same directory ran following command to create multicore image from terminal

./MulticoreImageGen LE 55 app 7 MCSPI_Master_j721e_evm_mcu2_1TestApp_release.rprc 4 MCSPI_Slave_j721e_evm_mcu1_0TestApp_release.rprc

Note;-

I found core Id from one of the thread as below

../../../../tools/multicoreImageGen/bin/MulticoreImageGen LE 55 app 0 sbl_baremetal_boot_test_j721e_evm_mpu1_0TestApp_release.rprc 1 sbl_baremetal_boot_test_j721e_evm_mpu1_1TestApp_release.rprc 4 sbl_baremetal_boot_test_j721e_evm_mcu1_0TestApp_release.rprc 5 sbl_baremetal_boot_test_j721e_evm_mcu1_1TestApp_release.rprc 6 sbl_baremetal_boot_test_j721e_evm_mcu2_0TestApp_release.rprc 7 sbl_baremetal_boot_test_j721e_evm_mcu2_1TestApp_release.rprc 8 sbl_baremetal_boot_test_j721e_evm_mcu3_0TestApp_release.rprc 9 sbl_baremetal_boot_test_j721e_evm_mcu3_1TestApp_release.rprc

So treated the cores as -->

0 --> mpu1_0                                                                                         1 --> mpu1_1                                                                     4 --> mcu1_0

5 --> mcu1_1                                                                                         6 --> mcu2_0                                                                     7 --> mcu2_1

8 --> mcu3_0                                                                                         9 --> mcu3_1

Please correct me if I am wrong.

Regards,

Tanvi

Hi Brijesh,

An update,I have tried MCU1_0 as Slave and MPU1_0 as master.Changed the instance in

static uint32_t SPI_test_get_instance (uint32_t testId, bool master)  

for master 3 and for  slave 1.

in that case "Some tests failed".

attached is the ScreenShot of output.

Regards,

Tanvi

Hi Tanvi,

Can you please check which tests failed? Because mcu1_0 and mpu1_0 are supported cores for this test example, with these cores, it should run fine. 

Also any changes in the example for making instance-3 (mcu1_0) as master and instance-1 (mpu1_0) as slave? 

Regards,

Brijesh

In addition, according to TRM,  MCSPI3 is connected as a master to MCU_MCSPI1 by default at power-up, so you dont require any additional configuration to use them internally. Just need to make sure they are configured correctly. 

Regards,

Brijesh

Hi Brijesh,

answers to your questions

1. "Also any changes in the example for making instance-3 (mcu1_0) as master and instance-1 (mpu1_0) as slave?" 

----> I didn't try this bcause the provided example from sdk worked fine with default instances i.e. 2 and 4

changes in example are made to work MPU1_0 as master and MCU1_0 as slave. those changes are listed in attached .txt file. 

As per the data sheet of TDA4VM -->

/*
	MCSPI3 and MCSPI4 include internal connectivity to MCSPI modules in the MCU domain, as follows:
	MCSPI3 is connected as a master to MCU_MCSPI1 by default at power-up. MCU_MCSPI1 and MCSPI3
	may be optionally mapped to external device pads.
	
	MCSPI4 is directly connected as a slave to MCU_MCSPI2 by default at power-up. MCSPI4 and
	MCU_MCSPI2 are not pinned out externally.
*/

Instance 3 is for mpu1_0 as master and instance 1 is for mcu1_0 as slave -->

The changes I made in file "main_mcspi_slave_mode.c" are --> 

/**********************************************************************

static uint32_t SPI_test_get_instance (uint32_t testId, bool master)
{
      uint32_t instance;

      /* Soc configuration structures indexing starts from 0. If the IP
       * instances start with 1, to address proper Configuration
       * structure index, McSPI Instance should be substracted with 1
       */
       if (master == (bool)true)
       {
           instance = (uint32_t)BOARD_MCSPI_MASTER_INSTANCE - 1;
       }
      else
       {
          instance = (uint32_t)BOARD_MCSPI_SLAVE_INSTANCE - 1;
       }
#if defined (SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200)
/*
* For AM65XX/J721E/J7200 SoC, master/slave test is set up to use
* McSPI 2 on the MCU domain for master and McSPI 4 on the
* Main domain for slave, for loopback test it uses default
* board McSPI instance
*/
      if (testId < SPI_TEST_ID_LOOPBACK)
      {
         if (master == true)
         {

               instance = 3U;     //changes done to make mpu1_0 as mater
//             instance = 2U;
         }
        else
        {

              instance = 1U;    //changes done to make mcu1_0 as slave
//            instance = 4U;
        }
        if ((testId == SPI_TEST_ID_TIMEOUT) ||
           (testId == SPI_TEST_ID_TIMEOUT_POLL))
        {
/*
* Timeout test is done in slave mode,
* on the McSPI 2 on MCU domain
*/
            instance = 1U;
       }

    }
#endif

return (instance);
}

/**********************************************************************************************************

The changes made in makefile at location
"ti-processor-sdk-rtos-j721e-evm-07_03_00_07/pdk_jacinto_07_03_00_29/packages/ti/drv/spi/example/mcspi_slavemode"

/*********************************************************************************************************************
ifeq ($(CORE), mpu1_0)
# Slave running on mpu1_0 core


#CFLAGS_SPI_MS = -DMCSPI_SLAVE_TASK                    <----------------------- COMMENTED THIS
#APP_MASTER_SLAVE = Slave                                          <----------------------- COMMENTED THIS
CFLAGS_SPI_MS = -DMCSPI_MASTER_TASK                <----------------------- LINES CHANGED
APP_MASTER_SLAVE = Master                                        <----------------------- LINES CHANGED

ifeq ($(SOC),$(filter $(SOC), am65xx))
# Slave uses local linker command file to avoid code/data memory conflict with master application
EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_INSTALL_PATH)/ti/drv/spi/example/mcspi_slavemode/am65xx/linker_mpu.lds
endif
else
# Master running on mcu1_0 core, use the common linker command file in build



#CFLAGS_SPI_MS = -DMCSPI_MASTER_TASK                    <----------------------- COMMENTED THIS
#APP_MASTER_SLAVE = Master                                            <----------------------- COMMENTED THIS
CFLAGS_SPI_MS = -DMCSPI_SLAVE_TASK                         <----------------------- LINES CHANGED
APP_MASTER_SLAVE = Slave                                                <----------------------- LINES CHANGED


ifeq ($(SOC),$(filter $(SOC), j721e j7200))
# Slave uses local linker command file to avoid code/data memory conflict with master application
ifeq ($(IS_BAREMETAL),yes)
EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_INSTALL_PATH)/ti/drv/spi/example/mcspi_slavemode/$(SOC)/linker_mcu.lds
else
EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_INSTALL_PATH)/ti/drv/spi/example/mcspi_slavemode/$(SOC)/linker_mcu_sysbios.lds

endif
endif

************************************************************************************************************************/

2.Can you please check which tests failed? Because mcu1_0 and mpu1_0 are supported cores for this test example, with these cores, it should run fine. 

----> as per the Screenshot Master(MPU1_0,instance 3) says non-dma interrupt mode pass and remaining test are failed

        and Slave(MCU1_0,instance 1) says non-dma interrupt mode failed.I have provided the ScreenShot in previous reply.

3. MCSPI3 is connected as a master to MCU_MCSPI1 by default at power-up, so you dont require any additional configuration to use them internally. Just       need to make sure they are configured correctly.

-----> can you please elaborate "configured correctly" ?does configuration means changes in pins,spi instances or changes in any of the component.mk or makefile?

 please guide further.

Thanks & Regards,

Tanvi 

One more question,

I went through

 https://e2e.ti.com/support/processors-group/processors/f/processors-forum/883597/tda4vmxevm-spi-driver-support-for-mcspi-in-main-domain

from this I could see SPI_soc.c involves MPU1_0 and MCU1_0 configurations only. 

I am using SDK 07.03.

are we supposed to do changes in SPI_soc.c? 

Regards,

Tanvi

Hi Tanvi,

Looking at the code, especially ti-processor-sdk-rtos-j721e-evm-08_00_00_12\pdk_jacinto_08_00_00_37\packages\ti\drv\spi\soc\j721e\SPI_soc.c, the array of spiInitCfg is of size only 5, although SoC supports more instances.. The first three instances are used for MCU domain and next 2 are for the main domain. What you need to do for main domain instance is to call SPI_socGetInitCfg API and then initialize Base address and rest of the config for this instance.. and then call SPI_socSetInitCfg.. Without this change, none of the test case would work in your test config.

Tanvi Gore said:

-----> can you please elaborate "configured correctly" ?does configuration means changes in pins,spi instances or changes in any of the component.mk or makefile?

What i meant here, can you please connect the CCS, take base address of the SPI you are using and check if the registers are configured correctly. I think they are not configured correctly, because in addition to changing instance id, you would also require to provide base address of the instances.. and also the correct interrupt number for the interrupt mode to work correctly. 

Regards,

Brijesh