Hi team,
Execution hardware: C7x hardware for TDA4
Features: Build custom layer for TIDL
Issue: The output of the previous layer should be the same value in theory as the corresponding input of the next layer, but the two are not identical.
The customer has some of assumptions:
1. DMA Transfer Issues: How many channel's are available for the 0703 DMA, and is there any change in the transfer configuration mechanism for the DMA?
2. Upper and lower links between the custom layers issue: How does this process pass data? Now that the trigger for the DMA has been determined and wait, the data is not transferred to the specified L2 address space. What is the reason for this? Will there be any hints from DMA? Is it performed properly? Note: Trigger has waited to ensure data is transferred.
Could you help check this case? Thanks!
Best Regards,
Cherry
