AM6442: GPMC 16 bit read issue

Rajesh Venkataraman

Part Number: AM6442

The GPMC registers are configured as below for the CS0

# devmem 0x3B000050
0x00000100
# devmem 0x3B000054
0x00000301
# devmem 0x3B000060
0x00601000
# devmem 0x3B000064
0x00080801
# devmem 0x3B000068
0x00000000
# devmem 0x3B00006c
0x08000800
# devmem 0x3B000070
0x00080808
# devmem 0x3B000074
0x88000380
# devmem 0x3B000078
0x00000E50

When we accesses the 16 bit device on the GPMC bus using the commands

# devmem 0x50000000 16
0x0002
# devmem 0x50000000 32
0x00000002

We see this on the scope for both 16 bit and 32 bit access. The pink is the clock, blue is chip select 0 and green is the wait signal.

For the 16 bit write we see this on the scope.

devmem 0x50000000 16 0x0002

Our device is 16 bit and the device size on the GPMC is set to 16. But why does the GPMC generate two chipselect cycle for a 16 bit read access. The data is read correctly for both 16 bit and 32 bit access. But it slows the read due to the extra access and the read may occur on a read to clear register. The extra access is for the next even address. For the 16 bit write access the GPMC generates one chip select cycle as expected. Is there a way to prevent this dummy chip select cycle on 16 bit reads?

over 3 years ago

0 Mark M over 3 years ago

TI__Mastermind 30140 points

Can you try using memory type "strongly ordered"?

See this post https://e2e.ti.com/support/processors-group/processors/f/processors-forum/316742/am335x-gpmc-phantom-chip-select-generation/1106520#1106520

Regards,
Mark

0 Rajesh Venkataraman over 3 years ago in reply to Mark M

Prodigy 10 points

Below are the options I have on Linux for the mmap() for this address. I tried the pgprot_noncached() and pgprot_device(). Both did not work. I also tried

__pgprot_modify(vma->vm_page_prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE));

And that did not work as well.

/*
* Mark the prot value as uncacheable and unbufferable.
*/
#define pgprot_noncached(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(Misolcpus=nohz,domain,CPUST_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
#define pgprot_writecombine(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
#define pgprot_device(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
#define pgprot_tagged(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
#define pgprot_mhp pgprot_tagged

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AM6442: GPMC 16 bit read issue