TMDS243GPEVM: DDR initialization hangs

Hi Joel,

How do you initialize your EVM? There two ways to do it:

1. Using the SBL_NULL. You will need to flash the SBL_NULL into either SD card or the OSPI flash

2. Using the launch_dmsc.js with JTAG under script console

If you are using the first one, you do not need to connect to DMSC. You can connect to R5F_0_0  directly and load the the program, since the DDR initialization is done by the SBL_NULL.

If you are using the launch_dmsc.js, can you try to use the SBL_NULL, since it is the recommended one. You can follow the instructions:

https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_01_00_36/exports/docs/api_guide_am64x/EVM_SETUP_PAGE.html#EVM_FLASH_SOC_INIT

Best regards,

Ming 

Hi Ming,

Thank you for your reply.

Yes, I have been using SBL_NULL.  Below is a screen shot of output from hello_world example for EVM (not LP) including serial terminal window indicating proper operation of the boot loader and the example:

As you can see, it loads and runs as expected.  (This example does not use DDR4 memory)

Following is an attempt to load the "enet_lwip_cpsw_am243x-evm_r5fss0-0_freertos_ti-arm-clang" example which does use DDR4 memory

The console shows that the problem is writing to memory at 0x80000000.  This is ddr memory.

linker.cmd line 144. 

    DDR       : ORIGIN = 0x80000000 , LENGTH = 0x1000000

So, is the DDR4 memory initialized by the boot loader and if it is, why does this example fail?

Thanks in advance,

       Joel

Hi Joel,

I am positive that the DDR initialization is done in SBL_NULL. One way to verify it is that use "memory browser" to read/write to 0x80000000 manually after connect to R5F_0_0 core.

I also verified the "enet_lwip_cpsw_am243x-evm_r5fss0-0_freertos_ti-arm-clang" example on AM243x EVM. It builds, loads and runs fine on AM243x EVM. Are you using the SBL_ NULL from the mcu_plus_sdk_am243x_08_01_00_36\examples\drivers\boot\sbl_null\am243x-evm\r5fss0-0_nortos\ti-arm-clang\tiboot3.bin?

Looks like you are using the older SBL_NULL. Here is my UART display for the SBL_NULL:

Starting NULL Bootloader ...

DMSC Firmware Version 21.9.0--v2021.09 (Terrific Llam
DMSC Firmware revision 0x15
DMSC ABI revision 3.1

INFO: Bootloader_runCpu:150: CPU r5f1-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:150: CPU r5f1-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:150: CPU m4f0-0 is initialized to 400000000 Hz !!!
INFO: Bootloader_runCpu:150: CPU a530-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:150: CPU a530-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:202: CPU r5f0-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:202: CPU r5f0-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runSelfCpu:219: All done, reseting self ...

Best regards,

Ming

Hi Ming,

I tried flashing the SBL_NULL bootloader as you indicated in a previous post.  (following the instructions here: https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_01_00_36/exports/docs/api_guide_am64x/EVM_SETUP_PAGE.html#EVM_FLASH_SOC_INIT) 

These instructions were for AM64x EVM but I have AM243x EVM so I flashed the bootloader using the configuration found here:

C:\ti\mcu_plus_sdk_am243x_08_01_00_36\tools\boot\sbl_prebuilt\am243x-evm\default_sbl_null.cfg

Here is a screen shot of the results:

After switching boot mode back to OSPI and powering the board I see this on the serial port:

I attempted to load the "enet_lwip_cpsw_am243x-evm_r5fss0-0_freertos_ti-arm-clang.out" example which failed in the same manner as previously.

Next I attempted to use the memory browser as you suggested.  Memory writes to 0x80000000 failed (screen shot below):

Attempts to write to address in the 0x70000000 range were successful (Specifically writes to 0x70080000 and 0x70080004)

Please note that I am using mcu_plus_sdk_am243x_08_01_00_36.

Next I noticed your question:

"Are you using the SBL_ NULL from the mcu_plus_sdk_am243x_08_01_00_36\examples\drivers\boot\sbl_null\am243x-evm\r5fss0-0_nortos\ti-arm-clang\tiboot3.bin?"

So I loaded that binary file (tiboot3.bin) 

This was successful but memory browser still fails to write to DDR memory.

So, I'm out of ideas.  Any help will be greatly appreciated.

     Thanks, Joel

Hi Joel,

That is weird. There one more thing you can try:

1. Copy the mcu_plus_sdk_am243x_08_01_00_36\examples\drivers\boot\sbl_null\am243x-evm\r5fss0-0_nortos\ti-arm-clang\tiboot3.bin to the microSD card (16GB) comes with the AM243x EVM

2. Insert the microSD card to the microSD slot.

3. Set the boot mode to boot from SD card

4. Power on the AM243x EVM. The UART should display the same info as the OSPI flash boot. 

Then try to access to the 0x80000000.

Best regards,

Ming

Hi Ming,

Thanks again for your suggestion.  I copied the file to the SD card, changed the boot mode, and power up the EVM.  The results are the same as UART boot.  Same message on serial console and still cannot r/w to DDR memory at 0x80000000.  Just to make sure that the board is booting from SD I removed the card and powered up the board.  Result: no boot message on serial console.  Next I reinserted the SD card & powered up.  Boot message appears as expected but still no R/W of DDR.

Thought I'd try something different.  I booted from SD card, connected to DMSC (cortex M3) then connected cortex R5_0_0. (possibly I connected R5 before M3, Can't remember which came first but probably R5 was first)

  Next I tried to R/W 0x80000000.  This time it worked. I could modify DDR memory.  See screen shot below.  

Console output when connecting M3:

DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000].
DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors
DMSC_Cortex_M3_0: GEL Output: Bootvectors configured.
DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: All PLLs programmed.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress...
DMSC_Cortex_M3_0: GEL Output: Powering up MAIN domain peripherals...
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_4B
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_8B
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ADC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUGSS
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPMC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SA2UL
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CPSW3G
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW done.
DMSC_Cortex_M3_0: GEL Output: Powering up all MAIN domain peripherals done.
DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals.
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TEST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_M4F
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F done.
DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals done.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!
DMSC_Cortex_M3_0: GEL Output:

Here is a screen shot of R/W to DDR (also showing debug connections):

At this point I tried to load the example application's .out file.  This failed and I had to reset and reboot.

Reading and writing DDR only worked one time.  Since then I have not been able to duplicate this ability to R/W DDR.

Still hoping that you can come up with a solution.

                  Joel

Hi Joel,

It turns out I was wrong about the DDR initialization for SBL_NULL which does not call the DDR_init(). It does call DDR_init() for SBL_SD and SD_UART though. If you are using SBL_NULL, you still need to following the steps in https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/08_01_00_36/exports/docs/api_guide_am243x/EVM_SETUP_PAGE.html#DDR_INIT to do the DDR initialization.

Best regards,

Ming

Hi Ming,

I retried the steps you suggested from the API guide. The results: 

The DDR initialization script hangs at the same point as originally reported in my first post about this question on 10 Dec.  (see above)

Note that this time I have not connected DMSC Cortex M3.  The reason I had previously tried connecting the DMSC was your response to a question raised by Krasi Gichev. Here is a link to that question:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1023345/tmds243gpevm-ddr4-init-fails-on-am243x-gpevm/3783148?tisearch=e2e-sitesearch&keymatch=%25252520user%2525253A86242#3783148

Following this advice to connect the DMSC processor used to work.  I could actually download into DDR memory.  At the time I was using mcu_plus_sdk_am243x_08_01_00_14.  The problem with GEL script hanging started when I ugraded to   mcu_plus_sdk_am243x_08_01_00_36 and at the same time upgraded the Sitara support package to the latest.  Since then the DDR initialization script always hangs.

Your thoughts would be appreciated.

       Joel

Hi Joel,

As a last resort, you may want to try to use the CCS script to initialize the EVM and DDR, although it is not a recommended way:

AM64x MCU+ SDK: EVM Setup (ti.com)

Best regards,

Ming

Hi Ming,

I have tried your 'Last Resort' solution with the following results:

1. Set environment variable

2.  Run the script.  Here are the various consoles:

Scripting Console:

Target Configuration CIO:

Target Configuration:

DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000].
DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors
DMSC_Cortex_M3_0: GEL Output: Bootvectors configured.
DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: All PLLs programmed.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress...
DMSC_Cortex_M3_0: GEL Output: Powering up MAIN domain peripherals...
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_4B
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_8B
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ADC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUGSS
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPMC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SA2UL
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CPSW3G
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW done.
DMSC_Cortex_M3_0: GEL Output: Powering up all MAIN domain peripherals done.
DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals.
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_M4F
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F done.
DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals done.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!
DMSC_Cortex_M3_0: GEL Output:
DMSC_Cortex_M3_0: GEL Output: M4F WFI Vector set into IRAM.

Note here that the screen shot found in AM64x MCU+ SDK: EVM Setup shows DDR initialization of the being performed by the CCS script (below) but the output I see here is as above with no DDR init:

Continuing on  with the suggestion I next run the AM24_DDR_Initialization_ECC_Disabled script.

Note that it hangs at the same point as previous attempts/suggestions:

As you can see, this problem has not been resolved.  I'll repeat the clue I mentioned in a previous reply (18-12-2021):

Following this advice to connect the DMSC processor used to work.  I could actually download into DDR memory.  At the time I was using mcu_plus_sdk_am243x_08_01_00_14.  The problem with GEL script hanging started when I ugraded to   mcu_plus_sdk_am243x_08_01_00_36 and at the same time upgraded the Sitara support package to the latest.  Since then the DDR initialization script always hangs.

Perhaps there is a mismatch between the Sitara support package and the SDK version?

Your thoughts would be appreciated,

                              Joel

Hi Joel,

I checked the difference between the 08.01.00.14/tools and 08.01.00.36/tools, the only difference is the MCU+ SDK install path and the SYSFW. If that is the problem, then you can use the 08.01.00.14/tools for launch_dmsc.js for now.

The issue is I cannot reproduce the same error on my board and the 08.01.00.36.

Best regards,

Ming

Hi Joel,

I finally figured out the root cause of the DDR initialization issue you reported.

The SBL_NULL for AM243x EVM and AM64x EVM are different, while the sbl_null_am64x-evm_r5fss0-0_nortos_ti-arm-clang does have the DDR initialization included and the sbl_null_am243x-evm_r5fss0-0_nortos_ti-arm-clang DOES NOT have the DDR initialization. That is why the sbl_null.release.tiimage (tiboot3.bin) in C:\ti\mcu_plus_sdk_am64x_08_01_00_36\tools\boot\sbl_prebuilt\am64x-evm\ made the DDR working. The sbl_null.release.tiimage (tiboot3.bin) in C:\ti\mcu_plus_sdk_am243x_08_01_00_36\tools\boot\sbl_prebuilt\am243x-evm\ does not make the DDR working.

I will file a bug against the SBL_NULL for AM243x EVM. At the same time, you can use the sbl_null.release.tiimage (tiboot3.bin) from MCU+ SDK 08.01.00.36 for OSPI or SD boot. This is a workaround and I have verified it on AM243x EVM.

Wish you have Merry Christmas and Happy New Year.

Best regards,

Ming

Hi Ming,

Thank you for your reply.  Before receiving the above I uninstalled CCS then reinstalled Version: 10.4.0.00006.  At this point I was able to:

1. Connect M3 processor

2. Connect R5_0_0

3. Run DDR init script

4. Read/Write memory at 0x80000000 using the memory browser

5. Import the example from mcu_plus_sdk_am243x_08_01_00_14 , compile/link it successfully

6. Load it into memory (at 0x80000000) 

7. Verify that it actually loaded by using the memory browser.

8. It did NOT execute properly but that's another issue.

The above verified that the DDR memory was still functional.

I'll try your workaround next and all going well you get a 'resolved' tick.

Thanks for finding this issue. I'm now well on the way to regaining my sanity.

Many thanks,

     Joel

Hi Ming,

Could you please provide more detail for your workaround.  I have tried flashing OSPI with 

C:\ti\mcu_plus_sdk_am243x_08_01_00_36\tools\boot\sbl_prebuilt\am243x-evm\sbl_null.release.tiimage

then booting from OSPI,  connecting the R5_0_0 and running the DDR init script.  Doesn't work.

Also tried booting from OSPI, connect the M3 then the R5 and running DDR init script.  Doesn't work.

----------------------------------------

Tried flashing OSPI withC:\ti\mcu_plus_sdk_am243x_08_01_00_14\tools\boot\sbl_prebuilt\am243x-evm\sbl_null.release.tiimage

Then boot from OSPI, connect R5 and run DDR init script.  Doesn't work

Tried boot from OSPI, connect M3, Connect R5, run DDR init script.  Doesn't work.

So, which bootloader did you use and what procedure did you use to connect processors and run script??

Thanks again,

      Joel 

Hi Joel,

Sorry for the confusion. You will need to download and install the MCU+ SDK 08.01.00.36 for AM64x from the following URL: 

MCU-PLUS-SDK-AM64X_08.01.00.36 | TI.com

then use the sbl_null.release.tiimage (tiboot3.bin) in C:\ti\mcu_plus_sdk_am64x_08_01_00_36\tools\boot\sbl_prebuilt\am64x-evm\ to either boot from SD card or flash it into he OSPI flash. In other words, replace the C:\ti\mcu_plus_sdk_am243x_08_01_00_36\tools\boot\sbl_prebuilt\am243x-evm\sbl_null.release.tiimage with this one.

Best regards,

Ming

Well, this is progress but still some questions.  I flashed OSPI with C:\ti\mcu_plus_sdk_am64x_08_01_00_36\tools\boot\sbl_prebuilt\am64x-evm\sbl_null.release.tiimage.  Subsequently booting from OSPI results in this output on the terminal:

All good so far, AM64 bootloader runs on AM243x board.  Next (without running the DDR init script) I try filling the first 10 words of DDR memory with 0xa5a5a5a5. This  is successful in spite of the console output indicating that I should run the script:

---------------------------------------------

Next I load the project output (.out file).  This looks to be successful:

------------------------------------------------------------------------------------------

After running the application there is no output on the terminal screen so I suspend execution on R5_0_0 with this result:

---------------------------------------------------------------

So, it looks like the DDR4 memory is initialized by the boot but gel file is reporting it as not initialized.  Also, DDR4 memory is working.  However, the example application is not working properly with the expected output on the terminal window. 

This leaves me wondering if I need to use the application from C:\ti\mcu_plus_sdk_am64x_08_01_00_36 rather than C:\ti\mcu_plus_sdk_am243x_08_01_00_36.  So, I tried importing the project from mcu_plus_sdk_am64x_08_01_00_36 but the import failed.

Which example application did you use?

Thanks again,

        Joel

Hi Joel,

I will still use the examples from the MCU+ SDK 08.01.00.36 for AM243x. The reason to use the BSL_NULL from AM64x is just a workaround for DDR initialization. It seems working OK, at least you can access the DDR without using GEL file. Since you are using the SBL_NULL from OSPI flash, so you do not have to use any GEL file for R5F_0_0 core nor the launch_dmsc.js anymore. You can delete the GEL file from the R5F_0_0. After the CCS target configuration file launch, you can connect to R5F_0_0 directly (no need to connect to DMSC first or run launch_dmsc.js from script console.

then load your application code directly.

From your screen capture, it looks like your code is FreeRTOS based and the idle task is running when you halt R5F_0_0 core. You can single step through your application code and make sure your code is running OK. You can also use the "Tools" --> "Runtime Object View" to look in the task status, interrupts and semaphores etc. in CCS.

The other way is to enable the CCS log (in Debug Log of example.syscfg) to confirm you application is running correctly.

Merry Christmas and Happy New Year!

Best regards,

Ming

Hi Ming,

The Task create issue in my previous reply was bogus.  It was my mistake in sysconfig file.

However, there may be a problem related to this workaround.  

The example project 'enet_lwip_cpsw_am243x-lp_r5fss0-0_freertos_ti-arm-clang' runs as expect on the LP board

However, when using the EVM board and the boot workaround as suggested above  I never get a local IP assigned or a link_callback == UP message.

Could this be related to the using the AM64 boot code.  In other words is it possible that the LP boot code does some ENET initialization that the AM64-EVM boot code (workaround) does not? 

Any other comments you may have about this issue would be greatly appreciated.

Thanks,

       Joel

Hi Joel,

I did not see any differences in SBL_NULL for AM64x EVM and AM243x EVM regarding to the ENET initialization, so I doubt that is the root cause. It is probably the ENET example differences caused the problem. I did the comparison of the example.syscfg between the AM243x EVM and the AM64x EVM. There are some differences:

In fact, you may try the ENET example in MCU+ SDK for AM64x EVM. it should work on AM243x EVM, because the AM243x EVM is the same as the AM64x EVM.

Best regards,

Ming

Hi Ming,

I tried using the AM64x EVM example on the AM243x EVM board as you suggested.  Good news, it linked and DHCP assigned an IP address.  However there still seems to be a problem.  I tried pinging the EVM board with the following results:

For comparison I loaded up my LP board with the same example with the following results:

Note that this was a side by side comparison.  I used the same cat6 cable connected to the same ethernet switch connection. Both boards were powered and executing the example code at the same time.  I just pinged the EVM board, moved the cable to the LP board and pinged it.

Any ideas why the the erratic performance?

Thanks,

     Joel

Thanks for all your help with the DDR issue.  I will post a new question.

Joel