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uPP of C6746

Sheri Zhuang
Prodigy 20 points
Other Parts Discussed in Thread: ADS8558, ADS7864

Hi,

C6746 DSP supports universal parallel port (uPP). I thought we can use it to control a ADC with parallel interface, for example, ADS8558 or even ADS7864.

The uPP is a dedicated control interface designed to interface cleanly with high speed ADC. As you can see from the time diagram, there are only 4 control signals (CLK, CH_start, CH_enable, CH_wait) and 16 data lines. The 16-bit data can be sent back to the DSP continuously. An internal DMA controller is included in uPP to maximize throughput and minimize cpu overhead.

However, after checking the uPP user guide in more detail, it becomes rather confusing if the uPP can be used to control a parallel ADC at all. I can see the uPP can be used to interface with a DAC since the control signals are being driven by the transmitter which is the uPP of the C6746. However, if we want to use the uPP to interface with a parallel ADC, the control signals (CLK, CH_start, CH_enable) would have to be driven by the ADC. Even though the C6746 data sheet said that uPP can be used to inetrface with a ADC, no example were given as how to arrange the interface. Can TI tell us if the uPP of C6746 can really be used to control a parallel ADC for high speec data transfer from ADC to the DSP? If yes, can you give a example arrangement for the circuit design?

Thanks.

Sheri

  • 0
    TI__Expert 8890 points

    Sheri,

    It's true that the uPP control signals (excluding WAIT) are driven by the transmitter.  However, in receive mode you can program the UPICR register to ignore the ENABLE and START signals if you want to simplify your connections.  In that case, the only control signal you will need to provide to the uPP receive channel is a clock with an appropriate frequency.  This can be generated by an external chip, or you can use the clock generated by the other uPP channel if it is operating in transmit mode.

    Hope this helps.

  • 0 in reply to Joe Coombs
    Prodigy 20 points

    Joe,

    We want to use a 6-channel ADC like ADS8558 or even ADS7864. I think the chip select (CS_) can be pull-low all the time. The RD_ (read) signal can be driven by the other uPP channel to control the ADC and drive the clock input of the uPP at the same time.

    There is also a busy output from ADC which will be in a defined high state (or low state, depends on ADC) when the ADC is in conversion. This was used to generate a interrupt to tell the DSP when to come and read the data from the ADC. Can we use this signal as the CH_enable siganl for the uPP? Would the timing be okay for this arrangement?

    It seems to me this may work out for ADS8558.

    ADS7864 samples all 6 channels at the same time but only convert two channels at a time. We run this ADC in cycle mode. Hold_A_, Hold_B_ and Hold_C_ signals also need to be controlled to allow simultaneous sampling on all 6 channels. In the current design, they are controlled by one timer output from the DSP. Somehow the DSP C6746 has to generate this siganl as well for the ADC.

    Could you please let me know if my understanding is correct?

    Thanks.

    Sheri

     

  • 0 in reply to Sheri Zhuang
    TI__Expert 8890 points

    Sheri,

    Of the two ADCs you reference, I think the ADS7864 may be a better fit for uPP based on the signal descriptions.  However, you will probably need additional logic to make this work since both ADCs seem to require additional control signals that are not part of the uPP protocol.

    Here is an example of an ADC that would interface more cleanly with uPP.  Note that the timing diagram basically consists of clock and data signals only.