Hello Experts,
We are currently investigating DDR3 data masking usage in our application.
According to TDA3 TRM:
EMIF controller supports 8 words burst length for DDR3 memory.
L3_MAIN interconnect port of EMIF has 128-bit data bus width.
We have 2 scenarios of writing to external RAM:
1. Writing from M4 IPU cache memory.
2. Writing from peripheral device e.g SPI using EDMA.
In case of first scenario, cache line size is 256 bit, so it matches DDR3 burst length (8x32-bit).
Does EMIF assure that singe cache line write is packed into single DDR3 burst transfer?
This would mean that data mask is not used at all when cache lines are written back to external RAM.
How EMIF will split data transfers towards DDR3 in case of EDMA?
Our problem originates from ECC topic, but ECC which is handled in DDR chip internally.
Memory supplier implements ECC only for complete 8 word write burst (data masking is not used).
We are trying now to find a method to prove in which use cases EMIF is not using data masking (which means for us that ECC mechanism is working on DDR chip side).
Hardware approach to check data mask line with scope seems to be not feasible for us.
Now we need confirmation from TI if based on TDA3 interconnect statistics we can judge whether EMIF will raise data mask or not.
Or maybe if there is other method that we can use to evaluate data masking usage.
Thanks and regards,
Milosz
