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DRA821U: IPC from QNX on A72 to RTOS on mcu1_0/1 (MCU domain)

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

We need to communicate IPC from QNX on A72 to RTOS on mcu1_0/1 (MCU domain).

I tried to build and run from SD according to SDK examples but the board crashed or I got no outputs.

Where can I find working step-by-step instructions to change, build and run the system?

 

EVMs: Jacinto J721EXCP01EVM and J7200XSOMG01EVM DRA821

SDKs j7200:

08_00_12 RTOS

08_00_00 QNX

08_00_05 Linux

BSP: BSP_ti-j7200-evm_br-710_be-710_SVN934683_JBN6.zip

Build environments (from ~/ti-processor-sdk-rtos-j7200-evm-08_00_00_12/):

export PSDK_RTOS_PATH=${PWD}

export PSDK_QNX_PATH=${PSDK_RTOS_PATH}/psdkqa

export PDK_VERSION=pdk_j7200_08_00_00_37

export PDK_PATH=${PSDK_RTOS_PATH}/${PDK_VERSION}

export QNX_BASE=/home/$USER/qnx710

export QNX_BSP_NAME=BSP_ti-j7200-evm_br-710_be-710_SVN934683_JBN6.zip

export QNX_BSP_PATH=${QNX_BASE}/bsp

export QNX_BSP_VERSION=710_SVN933027_JBN3

export QNX_SDP_VERSION=710

export BUILD_QNX_A72=yes

export PROFILE=release

export BOARD=j7200_evm

Example attemps to make EVM work

(paragraph numbers from “Processor SDK QNX J7200”):

-----------------------------------------------------------------------------------------------

3.2.2. Step 2: Copy files to the SD Card - QNX + SBL BootApps – looks Ok

ipc_test

IPC_echo_test (core : mpu1_0) .....

responderFxn will stay active. Please use ctrl-c to exit the test when finished.

SendTask4: mpu1_0 <--> mcu2_1, Ping- 10, pong - 10 completed

SendTask3: mpu1_0 <--> mcu2_0, Ping- 10, pong - 10 completed

-----------------------------------------------------------------------------------------

3.2.3. Step 2a: Copy files to the SD Card - QNX + SPL-Uboot

(With commands correction)

Failed on start.

Output:

U-Boot SPL 2021.01-g53e79d0e89 (Aug 07 2021 - 08:12:48 +0000)

Model: Texas Instruments K3 J7200 SoC

Board: J7200X-PM2-SOM rev E6

SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')

Trying to boot from MMC2

Starting ATF on ARM64 core...

NOTICE:  BL31: v2.5(release):08.00.00.004-dirty

NOTICE:  BL31: Built : 07:25:50, Aug  7 2021

U-Boot SPL 2021.01-g53e79d0e89 (Aug 07 2021 - 07:28:31 +0000)

Model: Texas Instruments K3 J7200 SoC

Board: J7200X-PM2-SOM rev E6

SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')

Detected: J7X-BASE-CPB rev E3

Detected: J7X-VSC8514-ETH rev E2

Trying to boot from MMC2

am654_sdhci sdhci@4fb0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19

U-Boot 2021.01-g53e79d0e89 (Aug 07 2021 - 07:28:31 +0000)

SoC:   J7200 SR1.0

Model: Texas Instruments K3 J7200 SoC

Board: J7200X-PM2-SOM rev E6

DRAM:  4 GiB

Flash: 0 Bytes

MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1

Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial@2800000

Out:   serial@2800000

Err:   serial@2800000

Detected: J7X-BASE-CPB rev E3

Detected: J7X-VSC8514-ETH rev E2

Net:   am65_cpsw_nuss_slave ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000

eth0: ethernet@46000000

Hit any key to stop autoboot:  0

switch to partitions #0, OK

mmc1 is current device

SD/MMC found on device 1

Failed to load 'boot.scr'

556 bytes read in 3 ms (180.7 KiB/s)

Loaded env from uEnv.txt

Importing environment from mmc1 ...

Running uenvcmd ...

gpio: pin gpio@22_17 (gpio 126) value is 1

gpio: pin gpio@22_16 (gpio 125) value is 0

k3_r5f_rproc r5f@41000000: Core 1 is already in use. No rproc commands work

k3_r5f_rproc r5f@41400000: Core 2 is already in use. No rproc commands work

6782412 bytes read in 73 ms (88.6 MiB/s)

Load Remote Processor 2 with data@addr=0x82000000 6782412 bytes: Success!

4792548 bytes read in 52 ms (87.9 MiB/s)

Load Remote Processor 3 with data@addr=0x82000000 4792548 bytes: Success!

8349640 bytes read in 90 ms (88.5 MiB/s)

## Starting application at 0x80080000 ...

MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519

cpu0: MPIDR=80000000

cpu0: MIDR=411fd080 Cortex-A72 r1p0

cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT

cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1

cpu0: L1 Icache 48K linesz=64 set/way=256/3

cpu0: L1 Dcache 32K linesz=64 set/way=256/2

cpu0: L2 Unified 1024K linesz=64 set/way=1024/16

Loading IFS...decompressing...done

cpu1: MPIDR=80000001

cpu1: MIDR=411fd080 Cortex-A72 r1p0

cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT

cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1

cpu1: L1 Icache 48K linesz=64 set/way=256/3

cpu1: L1 Dcache 32K linesz=64 set/way=256/2

cpu1: L2 Unified 1024K linesz=64 set/way=1024/16

System page at phys:0000000080011000 user:ffffff8040254000 kern:ffffff8040251000

Starting next program at vffffff80600883c0

All ClockCycles offsets within tolerance

Welcome to QNX Neutrino 7.1.0 on the TI J7200 EVM Board!!

Starting random service ...

start serial driver

start i2c driver

Starting MMC/SD memory card driver... eMMC

Starting MMC/SD memory card driver... SD

Starting XHCI driver on USB3SS0

ERROR:   Unhandled External Abort received on 0x80000000 from S-EL1

ERROR:   exception reason=0 syndrome=0xbf000000

Unhandled Exception from EL0

x0             = 0x00000049c4648bd0

x1             = 0x0000000000000000

x2             = 0x0000001028c30000

x3             = 0x0000000000000000

x4             = 0x0000001028c30000

x5             = 0x0000001028c30000

x6             = 0x0000000000000000

x7             = 0x0000000000000000

x8             = 0x000000000000000c

x9             = 0x0000000000010001

x10            = 0x0000000000000b00

x11            = 0x0000000000010000

x12            = 0x0000000000000000

x13            = 0x0000000000000040

x14            = 0x0000005037afd36d

x15            = 0x0000000000000000

x16            = 0x00000039fe6c6988

x17            = 0x00000039fe65aef0

x18            = 0x0000005037afd2bd

x19            = 0x00000049c4648bd0

x20            = 0x00000049c4648bd0

x21            = 0x00000049c4648ca0

x22            = 0x0000000000010000

x23            = 0x00000039fe703b00

x24            = 0x00000039fe703000

x25            = 0x00000039fe719160

x26            = 0x00000049c4648c10

x27            = 0x0000002e91a3d3d0

x28            = 0x0000005037afdb60

x29            = 0x0000005037afd8b0

x30            = 0x00000039fe6fd928

scr_el3        = 0x000000000000073d

sctlr_el3      = 0x0000000030cd183f

cptr_el3       = 0x0000000000000000

tcr_el3        = 0x0000000080803520

daif           = 0x00000000000002c0

mair_el3       = 0x00000000004404ff

spsr_el3       = 0x0000000000000000

elr_el3        = 0x00000039fe6faa38

ttbr0_el3      = 0x0000000070010c00

esr_el3        = 0x00000000bf000000

far_el3        = 0x0000000000000000

spsr_el1       = 0x0000000080000000

elr_el1        = 0x00000039fe65af00

spsr_abt       = 0x0000000000000000

spsr_und       = 0x0000000000000000

spsr_irq       = 0x0000000000000000

spsr_fiq       = 0x0000000000000000

sctlr_el1      = 0x0000000034d5db1d

actlr_el1      = 0x0000000000000000

cpacr_el1      = 0x0000000000000000

csselr_el1     = 0x0000000000000002

sp_el1         = 0xffffff80830df000

esr_el1        = 0x0000000056000051

ttbr0_el1      = 0x000d0008f79d6000

ttbr1_el1      = 0x000000008000b000

mair_el1       = 0xff000044eeaa0400

amair_el1      = 0x0000000000000000

tcr_el1        = 0x00000014b5983599

tpidr_el1      = 0x0000000000000000

tpidr_el0      = 0x0000000000000000

tpidrro_el0    = 0x0000005037afdf30

par_el1        = 0x0000000000000000

mpidr_el1      = 0x0000000080000000

afsr0_el1      = 0x0000000000000000

afsr1_el1      = 0x0000000000000000

contextidr_el1 = 0x0000000000000000

vbar_el1       = 0xffffff8060089000

cntp_ctl_el0   = 0x0000000000000000

cntp_cval_el0  = 0x0000000000000000

cntv_ctl_el0   = 0x0000000000000005

cntv_cval_el0  = 0x0000000036370e02

cntkctl_el1    = 0x0000000000000002

sp_el0         = 0x000000007000a3d0

isr_el1        = 0x0000000000000040

dacr32_el2     = 0x0000000000000000

ifsr32_el2     = 0x0000000000000000

cpuectlr_el1   = 0x0000001b00000040

cpumerrsr_el1  = 0x0000000000000000

l2merrsr_el1   = 0x0000000000000000

----------------------------------------

5.4. IPC Resource Manager

------------------------------------

Tring to build u-boot parts to communicate with mcu1_0.

“make -s ex02_bios_multicore_echo_testb_freertos BOARD=j7200_evm CORE=mcu1_0 -j2” – did nothing but we have "ex02_bios_multicore_echo_testb_freertos_mcu1_0_release_strip.xer5f" in folder

pdk_j7200_08_00_00_37/packages/ti/binary/ex02_bios_multicore_echo_testb_freertos/bin/j7200_evm/

Copy file to Linux SDK and building u-boot parts:

cp ${PSDK_RTOS_PATH}/pdk_j7200_08_00_00_XX/packages/ti/binary/ipc_echo_testb_freertos/bin/j7200_evm/ex02_bios_multicore_echo_testb_freertos_mcu1_0_release_strip.xer5f ${PSDK_LINUX_PATH}/board-support/prebuilt-images/ipc_echo_testb_mcu1_0_release_strip.xer5f

cd ${PSDK_LINUX_PATH}

make u-boot_clean

make u-boot

coping to SD.

After power on – no outputs.

  • Hi Arthur,

    What firmware image are you using for MCU1_0? You need to using ex02_bios_multicore_echo_testb firmware image for MCU1_0. The Linux SDK bootloader binaries are built by default with Linux compliant ipc_echo_testb_mcu1_0 firmware image.

    Please refer to the following FAQ for running IPC tests on QNX:

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1015234/faq-tda4vm-ipc_test-on-psdk-qnx-7-2-psdk-qnx-7-3

    regards

    Suman

  • My colleague Arthur asked about EVM j7200 examples that don't work.
    Your answer with attached link is for j721e - another board, another SDK.
    We cannot find working example how to build and run ipc test for mcu1_0/1 on J7200.

    Thanks beforehand,
    Igor

  • Hi Suman,

    Now I am using the new J7200  SDKs 08_01_00 and the situation has improved (I got missed in SDK osal\src files from TI PDK git).

    I was able to successfully run the IPC echo test for MCU0_1.

    I have questions:

    1.

    The ipc echo test succeeded only if I build tispl.bin with ex02_bios_multicore_echo_testb_freertos_mcu1_0_release_strip.xer5f (renamed to ipc_echo_testb_mcu1_0_release_strip.xer5f) and copy ex02_bios_multicore_echo_testb_freertos_mcu1_0_release.xer5f to $ {ROOTFS} / lib / firmware / (renamed to j7200-mcu -r5f0_0-fw).

    Is it normal that the same mcu firmware is present in two places? Maybe there is an easier way to build and run MCU0_1 firmware?

    2.

    In J7200 documentation describes only one example for MCU0_1 “ipc echo test” and there is a separate ex02_bios_multicore_echo_testb_freertos build.

    What are the limitations and special things to build and run examples for MCU0_1?

    3.

    Where can I find an example of big data transfer from MPU to MCU0_1?

    Thanks beforehand,
    Igor

  • Sorry, of course I meant mcu1 _0 (not MCU0_1).

    Most of the documentation in the "Processor SDK RTOS J7200 08_01_00" paragraph "8.3. MCU1_0 Application Development with SYSFW" refers to j721 EVM and “vision_apps” and is not relevant to j7200 EVM.

    Igor.

  • Hi Igor,

    (I got missed in SDK osal\src files from TI PDK git)

    Yeah, a patch was uploaded that needs to be applied on top of the default installation. This was also reported on this thread: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1066206/tda4vm-sdk8-1-qnx-rtos-build-failure

    1. The rename is strictly to do with the filename used by the default U-Boot build command. The U-Boot build uses the name ipc_echo_testb_mcu1_0_release_strip.xer5f, which is actually the Linux friendly MCU1_0 DM firmware image. This image won't work as is for QNX, and so you needed to use the QNX appropriate ex02_bios_multicore_echo_testb_freertos_mcu1_0_release_strip.xer5f firmware file.

    The copying of the firmware files into ${ROOTFS}/lib/firmware/ has to do with the default U-Boot early-boot env variables. This is not needed for MCU1_0 DM firmware (it is combined into the A72 SPL tispl.bin binary which is a FIT image), but is required for other R5Fs like MCU2_0 and MCU2_1.

    2. What link are you using for this statement?

    The PSDK QNX documentation for IPC Example does mention the correct images. 8.0 SDK provided two equivalent images, one with SYS/BIOS and the other with FreeRTOS. SYS/BIOS is completely descoped from 8.1 SDK onwards and only FreeRTOS images are provided.

    3. There isn't a ready-made big data transfer example available atm for J7200 atm, the existing example on J721E is based on Vision Apps. I will add a FAQ around this in the next couple of weeks.

    Thanks for pointing out the documentation gaps, I will follow up internally to get this fixed for the next SDK.

    regards

    Suman 

  • Hi Suman,

    Thanks for the answer.
    But I still don't know how I can build and run other pdk examples (eg. enet_lwip_example_freertos) on mcu1_0 in SPL boot mode.

    Can you explain to me please?

    Regards,

    Igor

  • Hi Igor,

    Is your original question about IPC with MCU1_0 resolved or do you still need clarification there?

    Running Ethernet of MCU1_0 is a separate topic from the thread title, suggest to open a new thread for that.

    regards

    Suman