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Seeking clarification on SDRC_STRBEN length and how to calculate length.

Caleb Austin
Prodigy 80 points
Other Parts Discussed in Thread: AM3517

 

With a current project, I am laying out DDR2 memory interface, following the guidelines listed the datasheet for the AM3517.

I have a question about how to calculate the length of trace to be used for signals STRBEN0 and STRBEN1. The data sheet states:

 

“CKB0B1 is the sum of the length of the CLK (the portion that goes to the memory associated with DQS0 and DQS1) plus the average length of the DQS0 and DQS1 differential pairs.”

 

Reading over the net, I find that there are example boards that do not have the same length as the datasheets states.  Is there someone that can provide more details on how to understand what STRBEN signal is doing?

What does the "portion" that goes to the memory... mean? CLK line from AM3517 to memory or from the junction of the T to the memory?

 

I have read over the errata and understand the limitations of using SRTBEN but would like to hear what others with experience working with this part can say about STRBENx.

 

Thanks,

Caleb

  • 0
    TI__Mastermind 41665 points

    Caleb Austin said:
    I have read over the errata and understand the limitations of using SRTBEN but would like to hear what others with experience working with this part can say about STRBENx.

    Before jumping into your questions, I wanted to point out that if you are implementing DDR2 on this device that advisory 1.1.43 from the errata recommends disabling the STRBENx signals anyway, so you don't need to route them at all, this was mentioned on another thread at http://e2e.ti.com/support/dsp/sitara_arm174_microprocessors/f/416/p/72293/264559.aspx#264559.

    Caleb Austin said:
    Reading over the net, I find that there are example boards that do not have the same length as the datasheets states.

    It is possible for the DDR interface to work outside of the specifications in the datasheet, and so there are certainly boards out there that do not follow the specs, but it is not recommended, and there is not much TI can do if it does not work in this case.

    Caleb Austin said:
    What does the "portion" that goes to the memory... mean? CLK line from AM3517 to memory or from the junction of the T to the memory?

    The goal of the STRBEN signal is to provide a timing feedback loop, so you want the signal coming out of STRBEN and back into the processor to be the length traveled by the signals associated with it, I believe what this is getting at is that you want one the distance of the clock in one run between the two parts (i.e. don't add in both sides of the T).