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DRA821U: U-boot question with ospi on dra821 custom board.

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821, TEST

Hi TI,

I have a problem with booting on my custom board. At first it seems that it can be written to FLASH successfully,

U-Boot SPL 2021.01-g53e79d0e89 (Aug 07 2021 - 07:28:31 +0000)
Model: Texas Instruments K3 J7200 SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -1
Trying to boot from SPI
cadence_spi spi@47040000: Can't get reset: -2
jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.


U-Boot 2021.01-g53e79d0e89 (Aug 07 2021 - 07:28:31 +0000)

SoC:   J7200 SR1.0
Model: Texas Instruments K3 J7200 SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -1
Board: J721EX-PM1-SOM rev E2
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -1
Net:   Could not get PHY for ethernet@46000000: addr 0
am65_cpsw_nuss_slave ethernet@46000000: phy_connect() failed
No ethernet found.

Hit any key to stop autoboot:  0
=> sf probe
cadence_spi spi@47040000: Can't get reset: -2
jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
SF: Detected s28hs512t with page size 256 Bytes, erase size 256 KiB, total 64 MiB
=> fatload mmc 1 ${loadaddr} tiboot3.bin; sf update $loadaddr 0x0 $filesize;
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
527381 bytes read in 8 ms (62.9 MiB/s)
device 0 offset 0x0, size 0x80c15
0 bytes written, 527381 bytes skipped in 0.24s, speed 20001412 B/s
=> fatload mmc 1 ${loadaddr} tispl.bin; sf update $loadaddr 0x100000 $filesize;
841164 bytes read in 12 ms (66.8 MiB/s)
device 0 offset 0x100000, size 0xcd5cc
0 bytes written, 841164 bytes skipped in 0.31s, speed 24610055 B/s
=> fatload mmc 1 ${loadaddr} u-boot.img; sf update $loadaddr 0x300000 $filesize;
1092428 bytes read in 16 ms (65.1 MiB/s)
device 0 offset 0x300000, size 0x10ab4c
0 bytes written, 1092428 bytes skipped in 0.40s, speed 26015029 B/s
=> boot
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
switch to partitions #0, OK
mmc1 is current device
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
SD/MMC found on device 1
Failed to load 'boot.scr'
0 bytes read in 2 ms (0 Bytes/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
19137024 bytes read in 774 ms (23.6 MiB/s)
43397 bytes read in 6 ms (6.9 MiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 000000008fef2000, end 000000008fffffff ... OK

Starting kernel ...

But when I try to write again, I used the "sf probe" command in u-boot prompt,it show "Failed to initialize SPI flash at 0:0 (error -2)" as below

U-Boot SPL 2021.01-g53e79d0e89 (Aug 07 2021 - 08:12:48 +0000)
Model: Texas Instruments K3 J7200 SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.5(release):08.00.00.004-dirty
NOTICE:  BL31: Built : 07:25:50, Aug  7 2021

U-Boot SPL 2021.01 (Dec 16 2021 - 09:31:53 +0800)
Model: Texas Instruments K3 J7200 SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2
am654_sdhci sdhci@4fb0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19


U-Boot 2021.01 (Dec 16 2021 - 09:31:53 +0800)

SoC:   J7200 SR1.0
Model: Texas Instruments K3 J7200 SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
Loading Environment from MMC... OK
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Net:   Could not get PHY for ethernet@46000000: addr 0
am65_cpsw_nuss_slave ethernet@46000000: phy_connect() failed
No ethernet found.

Hit any key to stop autoboot:  0
=> sf probe
cadence_spi spi@47040000: Can't get reset: -2
jedec_spi_nor flash@0: unrecognized JEDEC id bytes: f0, 00, 00
Failed to initialize SPI flash at 0:0 (error -2)
=>

We use prebulid u-boot image  with J7200 SDK V8.0 

Could you please give some advice for this question.

  • Hi Jay:

    cadence_spi spi@47040000: Can't get reset: -2
    jedec_spi_nor flash@0: unrecognized JEDEC id bytes: f0, 00, 00
    Failed to initialize SPI flash at 0:0 (error -2)

    There are 2 ways to debug the SPI Flash from SW perspective:

    #1. Read this https://blog.csdn.net/kickxxx/article/details/56012456

          You need to check mounted devices to see if there is SPI flash.

    #2. The error logs said there might have the problem on the SPI HW, may you check if the SF probe fail all the time?

    Thanks.

    BR Rio

  • Hi Jay,

    Please share the OSPI part that is being used on your custom board. Also have you taken care of any pin mux changes
    that were done on your custom board?

    Best Regards,
    Keerthy

  • Hi Keerthy,

    Our custom board is used S28HS512T, which is the same as evm board.

    We haven't changed pin mux,

    Is there any way to check where the problem is?

  • Jay,

    I observed your logs that was doing sf probe first time successfully:

    fatload mmc 1 ${loadaddr} tiboot3.bin; sf update $loadaddr 0x0 $filesize;
    i2c_write: error waiting for data ACK (status=0x116)
    pca953x gpio@22: Error reading output register
    527381 bytes read in 8 ms (62.9 MiB/s)
    device 0 offset 0x0, size 0x80c15
    0 bytes written, 527381 bytes skipped in 0.24s, speed 20001412 B/s
    => fatload mmc 1 ${loadaddr} tispl.bin; sf update $loadaddr 0x100000 $filesize;
    841164 bytes read in 12 ms (66.8 MiB/s)
    device 0 offset 0x100000, size 0xcd5cc
    0 bytes written, 841164 bytes skipped in 0.31s, speed 24610055 B/s
    => fatload mmc 1 ${loadaddr} u-boot.img; sf update $loadaddr 0x300000 $filesize;
    1092428 bytes read in 16 ms (65.1 MiB/s)
    device 0 offset 0x300000, size 0x10ab4c
    0 bytes written, 1092428 bytes skipped in 0.40s, speed 26015029 B/s

    None of the binaries were written.

    Can you try on a different board? To rule out any board specific issue?
    As the sf probe is failing consistently after the first time was successful I suspect some issue with the hardware.

    Best Regards,
    Keerthy

  • Hi Jay:

    #1.

    You can debug this OPSI function by the following:

    In this file, board-support/u-boot-2021.01+gitAUTOINC+53e79d0e89-g53e79d0e89/pinctrl/pinctrl-uclass.c
    This function: static int pinctrl_select_state_full(struct udevice *dev, const char *statename)

    #2.

    Why you have J721E board ID in the error log here?

    SoC: J7200 SR1.0
    Model: Texas Instruments K3 J7200 SoC
    EEPROM not available at 0x50, trying to read at 0x51
    Reading on-board EEPROM at 0x51 failed 1
    Board: J721EX-PM1-SOM rev E2

    BR Rio

  • Hi Rio,

    We have modified the board to J7200X-PM2-SOM rev E6, but still can't read the flash.

    U-Boot SPL 2021.01-g53e79d0e89 (Aug 07 2021 - 08:12:48 +0000)
    Model: Texas Instruments K3 J7200 SoC
    EEPROM not available at 0x50, trying to read at 0x51
    Reading on-board EEPROM at 0x51 failed 1
    Board: J721EX-PM1-SOM rev E2
    SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')
    EEPROM not available at 0x50, trying to read at 0x51
    Reading on-board EEPROM at 0x51 failed 1
    Trying to boot from MMC2
    Starting ATF on ARM64 core...
    
    NOTICE:  BL31: v2.5(release):08.00.00.004-dirty
    NOTICE:  BL31: Built : 07:25:50, Aug  7 2021
    
    U-Boot SPL 2021.01 (Dec 21 2021 - 16:46:37 +0800)
    Model: Texas Instruments K3 J7200 SoC
    ti_i2c_eeprom_am6_parse_record: Ignoring record id 17
    Board: J7200X-PM2-SOM rev E6
    SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')
    Detected: J7X-BASE-CPB rev E3
    Detected: J7X-VSC8514-ETH rev E2
    Trying to boot from MMC2
    am654_sdhci sdhci@4fb0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
    
    
    U-Boot 2021.01 (Dec 21 2021 - 16:46:37 +0800)
    
    SoC:   J7200 SR1.0
    Model: Texas Instruments K3 J7200 SoC
    Board: J7200X-PM2-SOM rev E6
    DRAM:  4 GiB
    Flash: 0 Bytes
    MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
    Loading Environment from MMC... OK
    In:    serial@2800000
    Out:   serial@2800000
    Err:   serial@2800000
    Detected: J7X-BASE-CPB rev E3
    Detected: J7X-VSC8514-ETH rev E2
    cdns,torrent serdes@5060000: Timeout waiting for CMN ready
    cdns,torrent serdes@5060000: PHY: Failed to power on serdes@5060000: -110.
    phy_power_on failed !!
    Net:   Could not get PHY for ethernet@46000000: addr 0
    am65_cpsw_nuss_slave ethernet@46000000: phy_connect() failed
    No ethernet found.
    
    Hit any key to stop autoboot:  0
    =>  sf probe
    cadence_spi spi@47040000: Can't get reset: -2
    jedec_spi_nor flash@0: unrecognized JEDEC id bytes: f8, 00, 00
    Failed to initialize SPI flash at 0:0 (error -2)
    =>

    Is there any other way to confirm the problem?

  • Hi Jay:

    I just found the TI has the OSPI flash patch in this week:

    https://git.ti.com/cgit/ti-u-boot/ti-u-boot/commit/?h=ti-u-boot-2021.01&id=b9979bc450883a3a1e92f4add22cdf8848c7c491

    You can cross reference this then port it onto J7200.

    BR Rio

  • Hi Keerthy:

    Customer has tested their OSPI flash by using CCS project, the results are posted onto here.

    Do you have any comments?

    BR Rio

  • Hi RIO

    (1)If We only probe the OSPI Flash during u-boot prompt , and continuing the probe action “WITHOUT” any writing to the flash.
    All probe actions are passed and no any problem.

    => sf probe
    cadence_spi spi@47040000: Can't get reset: -2
    jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
    k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
    k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
    SF: Detected s28hs512t with page size 256 Bytes, erase size 256 KiB, total 64 MiB

    (2)After We probe and write  the OSPI Flash during u-boot prompt, 

    Hit any key to stop autoboot:  0
    =>  sf probe
    cadence_spi spi@47040000: Can't get reset: -2
    jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
    k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
    k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
    SF: Detected s28hs512t with page size 256 Bytes, erase size 256 KiB, total 64 MiB
    => fatload mmc 1 ${loadaddr} tiboot3.bin; sf update $loadaddr 0x0 $filesize;
    i2c_write: error waiting for data ACK (status=0x116)
    pca953x gpio@22: Error reading output register
    527825 bytes read in 25 ms (20.1 MiB/s)
    device 0 offset 0x0, size 0x80dd1
    527825 bytes written, 0 bytes skipped in 4.438s, speed 121705 B/s
    => fatload mmc 1 ${loadaddr} tispl.bin; sf update $loadaddr 0x100000 $filesize;
    841620 bytes read in 39 ms (20.6 MiB/s)
    device 0 offset 0x100000, size 0xcd794
    841620 bytes written, 0 bytes skipped in 6.187s, speed 139227 B/s
    => fatload mmc 1 ${loadaddr} u-boot.img; sf update $loadaddr 0x300000 $filesize;
    1092828 bytes read in 50 ms (20.8 MiB/s)
    device 0 offset 0x300000, size 0x10acdc
    1092828 bytes written, 0 bytes skipped in 7.749s, speed 144357 B/s

    (3) we can uboot with ospi flash, and starting kernel  with  disable ospi dts in linux  

    U-Boot 2021.01 (Dec 21 2021 - 13:42:21 +0800)
    
    SoC:   J7200 SR1.0
    Model: Texas Instruments K3 J7200 SoC
    Board: J7200X-PM2-SOM rev E6
    DRAM:  4 GiB
    Flash: 0 Bytes
    MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
    Loading Environment from MMC... OK
    In:    serial@2800000
    Out:   serial@2800000
    Err:   serial@2800000
    Detected: J7X-BASE-CPB rev E3
    Detected: J7X-VSC8514-ETH rev E2
    
    U-Boot SPL 2021.01 (Dec 21 2021 - 13:42:24 +0800)
    Model: Texas Instruments K3 J7200 SoC
    Board: J7200X-PM2-SOM rev E6
    SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')
    Trying to boot from SPI
    Starting ATF on ARM64 core...
    
    NOTICE:  BL31: v2.5(release):08.00.00.004-dirty
    NOTICE:  BL31: Built : 07:25:50, Aug  7 2021
    
    U-Boot SPL 2021.01 (Dec 21 2021 - 13:42:21 +0800)
    Model: Texas Instruments K3 J7200 SoC
    Board: J7200X-PM2-SOM rev E6
    SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')
    Detected: J7X-BASE-CPB rev E3
    Detected: J7X-VSC8514-ETH rev E2
    Trying to boot from SPI
    cadence_spi spi@47040000: Can't get reset: -2
    jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
    
    
    U-Boot 2021.01 (Dec 21 2021 - 13:42:21 +0800)
    
    SoC:   J7200 SR1.0
    Model: Texas Instruments K3 J7200 SoC
    Board: J7200X-PM2-SOM rev E6
    DRAM:  4 GiB
    Flash: 0 Bytes
    MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
    Loading Environment from MMC... OK
    In:    serial@2800000
    Out:   serial@2800000
    Err:   serial@2800000
    Detected: J7X-BASE-CPB rev E3
    Detected: J7X-VSC8514-ETH rev E2
    cdns,torrent serdes@5060000: Timeout waiting for CMN ready
    cdns,torrent serdes@5060000: PHY: Failed to power on serdes@5060000: -110.
    phy_power_on failed !!
    Net:   Could not get PHY for ethernet@46000000: addr 0
    am65_cpsw_nuss_slave ethernet@46000000: phy_connect() failed
    No ethernet found.
    
    Hit any key to stop autoboot:  0
    switch to partitions #0, OK
    mmc0(part 0) is current device
    SD/MMC found on device 0
    Failed to load 'boot.scr'
    Failed to load 'uEnv.txt'
    i2c_write: error waiting for data ACK (status=0x116)
    pca953x gpio@21: Error reading output register
    GPIO: 'gpio@22_17' not found
    Command 'gpio' failed: Error -121
    i2c_write: error waiting for data ACK (status=0x116)
    pca953x gpio@21: Error reading output register
    GPIO: 'gpio@22_16' not found
    Command 'gpio' failed: Error -121
    k3_r5f_rproc r5f@41000000: Core 1 is already in use. No rproc commands work
    k3_r5f_rproc r5f@41400000: Core 2 is already in use. No rproc commands work
    634196 bytes read in 6 ms (100.8 MiB/s)
    Load Remote Processor 2 with data@addr=0x82000000 634196 bytes: Success!
    83148 bytes read in 4 ms (19.8 MiB/s)
    Load Remote Processor 3 with data@addr=0x82000000 83148 bytes: Success!
    19270144 bytes read in 66 ms (278.4 MiB/s)
    45773 bytes read in 3 ms (14.6 MiB/s)
    ## Flattened Device Tree blob at 88000000
       Booting using the fdt blob at 0x88000000
       Loading Device Tree to 000000008fef1000, end 000000008fffffff ... OK
    
    Starting kernel ...
    

    (4)Repeat the “Power OFF/ON “ several times , OSPI flash boot fail

    We probe OSPI Flash during u-boot prompt,the OSPI flash will be stuck .

    Hit any key to stop autoboot:  0
    =>  sf probe
    cadence_spi spi@47040000: Can't get reset: -2
    jedec_spi_nor flash@0: unrecognized JEDEC id bytes: f8, 00, 00
    Failed to initialize SPI flash at 0:0 (error -2)

    In this state, OSPI flash can't  access-able again.

    BR

    JAY

  • Hi Rio

    before fatload  ospi_phy_pattern.bin in new DRA821 custom board (ospi nor flash is access-able)

    => sf probe
    cadence_spi spi@47040000: Can't get reset: -2
    jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
    k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
    k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
    cadence_spi spi@47040000: PHY calibration failed: -2. Falling back to slower clock speeds.
    SF: Detected s28hs512t with page size 256 Bytes, erase size 256 KiB, total 64 MiB
    
    => fatload mmc 1 ${loadaddr} tiboot3.bin;
    523617 bytes read in 24 ms (20.8 MiB/s)
    =>  sf update $loadaddr 0x0 $filesize;
    device 0 offset 0x0, size 0x7fd61
    523617 bytes written, 0 bytes skipped in 3.36s, speed 176434 B/s
    => fatload mmc 1 ${loadaddr} tispl.bin; sf update $loadaddr 0x100000 $filesize;
    878264 bytes read in 39 ms (21.5 MiB/s)
    device 0 offset 0x100000, size 0xd66b8
    878264 bytes written, 0 bytes skipped in 6.101s, speed 147312 B/s
    =>  fatload mmc 1 ${loadaddr} u-boot.img; sf update $loadaddr 0x300000 $filesize;
    1092964 bytes read in 48 ms (21.7 MiB/s)
    device 0 offset 0x300000, size 0x10ad64
    1092964 bytes written, 0 bytes skipped in 7.474s, speed 149685 B/s

    fatload  ospi_phy_pattern.bin

    => fatload mmc 1 ${loadaddr} ospi_phy_pattern.bin
    128 bytes read in 2 ms (62.5 KiB/s)
    => sf update $loadaddr 0x3fc0000 $filesize
    device 0 offset 0x3fc0000, size 0x80
    0 bytes written, 128 bytes skipped in 0.8s, speed 13107 B/s

    my result of sf probe

    => sf probe
    jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
    cadence_spi spi@47040000: PHY calibration failed: -2. Falling back to slower clock speeds.
    SF: Detected s28hs512t with page size 256 Bytes, erase size 256 KiB, total 64 MiB
    
    => fatload mmc 1 ${loadaddr} tiboot3.bin; sf update $loadaddr 0x0 $filesize;
    523617 bytes read in 25 ms (20 MiB/s)
    device 0 offset 0x0, size 0x7fd61
    0 bytes written, 523617 bytes skipped in 0.17s, speed 26809190 B/s

    BR

    JAY

  • Hi RIO

    my result of sf probe and update same image again. you can find 0 bytes written for same  image

    =>  sf probe
    jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
    cadence_spi spi@47040000: PHY calibration failed: -2. Falling back to slower clock speeds.
    SF: Detected s28hs512t with page size 256 Bytes, erase size 256 KiB, total 64 MiB
    => fatload mmc 1 ${loadaddr} ospi_phy_pattern.bin
    128 bytes read in 2 ms (62.5 KiB/s)
    => sf update $loadaddr 0x3fc0000 $filesize
    device 0 offset 0x3fc0000, size 0x80
    0 bytes written, 128 bytes skipped in 0.8s, speed 11915 B/s
    => fatload mmc 1 ${loadaddr} tiboot3.bin; sf update $loadaddr 0x0 $filesize;
    523617 bytes read in 25 ms (20 MiB/s)
    device 0 offset 0x0, size 0x7fd61
    0 bytes written, 523617 bytes skipped in 0.16s, speed 28220200 B/s
    => fatload mmc 1 ${loadaddr} tispl.bin; sf update $loadaddr 0x100000 $filesize;
    878264 bytes read in 40 ms (20.9 MiB/s)
    device 0 offset 0x100000, size 0xd66b8
    0 bytes written, 878264 bytes skipped in 0.32s, speed 25695495 B/s
    => fatload mmc 1 ${loadaddr} u-boot.img; sf update $loadaddr 0x300000 $filesize;
    1092964 bytes read in 51 ms (20.4 MiB/s)
    device 0 offset 0x300000, size 0x10ad64
    0 bytes written, 1092964 bytes skipped in 0.40s, speed 26027793 B/s

    BR

    JAY

  • Hi Jay:

    #1. As long as there is no -2 error on the SPI log, it should be okay.

    #2. Or, you can write it onto different address.

          See the doc: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/07_03_00_05/exports/docs/linux/Foundational_Components/U-Boot/UG-QSPI.html

           The J7200 Layout is as the below.

    Flash Layout for OSPI

          0x0 +----------------------------+
              |     ospi.tiboot3(512K)     |
              |                            |
      0x80000 +----------------------------+
              |     ospi.tispl(2M)         |
              |                            |
     0x280000 +----------------------------+
              |     ospi.u-boot(4M)        |
              |                            |
     0x680000 +----------------------------+
              |     ospi.env(128K)         |
              |                            |
     0x6A0000 +----------------------------+
              |   ospi.env.backup (128K)   |
              |                            |
     0x6C0000 +----------------------------+
              |      ospi.sysfw(1M)        |
              |                            |
     0x7C0000 +----------------------------+
              |      padding (256k)        |
     0x800000 +----------------------------+
              |     ospi.rootfs(UBIFS)     |
              |                            |
    0x3FE0000 +----------------------------+
              |   ospi.phypattern (128k)   |
              |                            |
              +----------------------------+

    BR Rio

  • Hi RIO

    Update Test result

    We following doc to test OSPI read/write in uboot prompt
    - OSPI read/write normal with Power ON/OFF (>3sec) for 2 days.
    - OSPI read fail when quickly Power ON/OFF(<1sec)

    In this state, OSPI flash can't  access-able again.

    BR

    JAY

  • Hi Karan/Keerthy:

    If any comments, please help.

    Thanks.

    BR Rio

  • Jay/Rio,

    - OSPI read/write normal with Power ON/OFF (>3sec) for 2 days.
    - OSPI read fail when quickly Power ON/OFF(<1sec)

    Can you elaborate a bit on this? What is greater than 3 seconds? Is OSPI boot working?

    - Keerthy

  • Hi Keerthy:

    Yes, if the interval is > 3 sec, the OSPI is working well.

    BR Rio

  • Hi Rio/Jay,

    So basically  if the interval is > 3 sec, the OSPI is working well

    - OSPI read fail when quickly Power ON/OFF(<1sec)

    So is this high priority issue now? Since boot is working fine. What is the request here? Is it to investigate failure with < 1 Second restart?

    Best Regards,
    Keerthy

     

  • Hi Keerthy

    - OSPI read fail when quickly Power ON/OFF(<1sec)

    When OSPI read fail when quickly Power ON/OFF(<1sec), which means whenever Power ON/OFF , OSPI flash can't  access-able again anymore 

    We think this is high priority issue 

    BR

    JAY

  • Jay,

    Any other boot mode on your board that works on < 1S? Like eMMC/MMC-SD?
    Just want to check if this is specific to OSPI or other boot modes as well. This data point will help isolate some board level constraint.

    - Keerthy

  • Hi Keerthy J

    When OSPI boot fail and can't access again anymore whenever power on/off in this case, we switch to eMMC/MMC-SD boot mode , we can entry linux kernerl normal.

    BR

    JAY

  • Hi Keerthy:

    Foxconn did follow these steps:

    Step0: sf probe – Step1: fatload mmc 1 ${loadaddr} nor_spi_patterns.bin –

    Step2: sf update $loadaddr 0x3fc0000 $filesize –

    Step3: fatload mmc 1 ${loadaddr} tiboot3.bin; sf update $loadaddr 0x0 $filesize; –

    Step4: fatload mmc 1 ${loadaddr} tispl.bin; sf update $loadaddr 0x100000 $filesize; –

    Step5: fatload mmc 1 ${loadaddr} u-boot.img; sf update $loadaddr 0x300000 $filesize;

    But, to perform these steps, it cannot allow user to do the quick reset.

    The real situations are:

        A. If doing those steps as the above, this QSPI issue is gone.

        B. If doing the quick reset, Customer won't take those steps, so, this issue only appears when the "quick cold" reset.

         Any better comments?

    BR Rio

  • Rio/Jay,

    I am checking with our board experts. Please confirm that failure is when you power cycle the board in < 1 Second. If yes then it is
    expected behavior & we see hangs even on DRA821 EVM.

    - Keerthy