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66AK2H14: DDR3 controller

Bruno B
Expert 1290 points
Part Number: 66AK2H14


Hi

Some questions about the DDR3A interface, and descriptions from  SPRUHN7C document:

  • Is there a way to change the DDR3CLKOUP output drive and slew rate ?

  • Is the ACIOCR register operational ? how can we use it ? are there constraints about when to change the <31-30> bit values (before leveling? after leveling ? else?

  • same kind of question about ZQnCR0 register :
    • How to use ZDATA feature ?
    • we tried to force the same ZDATA values as the ones automatically retrieved from levelling in ZQnSR0 register , but this makes the core to crush.
    • to which impedance traces are related ZQ0CR0 , ZQ1CR0,ZQ2CR0, and ZQ3CR0 ?

With best regards,

Bruno

  • 0
    TI__Guru 55287 points

    Bruno,

    I am not aware of a way to change the DDR3CLKOUT drive and slew rate.  Generally, if you follow the DDR Layout guidelines appnote this should not be required.

    This appnote guides you through the recommended register configuration for the DDR3 interface.  The registers you are asking about are not recommended to be modified.

    Keystone II DDR3 Initialization

    Regards,
    Kyle