AM5728: Writes to GPMC peripheral are delaying interrupt service routine

Hi Sean,

Can you please share few details here:

1) Is any part of your GPMC read/write processing happening using interrupts or in the ISR context?
2) Also, can you please share what other interrupts are enabled in the system other than mailbox interrupts?

Regards,
Parth

Hi Parth,

To clarify, our software threads are all executing on the DSP. The ARM processor or other coprocessor cores of the AM572x are not running in our application.

1) The GPMC accesses causing the undesired ISR delay are all writes and are occurring in our "low priority" thread, which itself is a SWI. These GPMC writes are in a loop and are simply direct accesses by the DSP writing to the memory locations corresponding to CS0 of the GPMC peripheral. The ISR that is being delayed is our "high priority" thread, which is a HWI triggered by a Mailbox write. All GPMC accesses in our application are done directly by the DSP.

2) As far as interrupts go, we have a few threads launched by Mailbox interrupts as HWIs. We also utilize some GPIO interrupts to trigger EDMA transfers, but these do not involve the GPMC peripheral. We do not use any other interrupts.

Hi Sean,

Sean DeHarde said:

As far as interrupts go, we have a few threads launched by Mailbox interrupts as HWIs. We also utilize some GPIO interrupts to trigger EDMA transfers, but these do not involve the GPMC peripheral.

Can you please share the interrupt numbers you are using for these interrupts?

Regards,
Parth

Hi Parth,

The hardware interrupt (HWI) that is being delayed is utilizing DSP interrupt number 14 (the first argument to the *Hwi_create* function). This interrupt event's event ID is set to 50, which corresponds to IRQ crossbar output number 19. This IRQ crossbar output is configured to use Mailbox 2 user 1 interrupt corresponding to crossbar input number 238.

The code being interrupted by the above hardware interrupt is simply a posted SWI. There is no DSP interrupt number associated with it.

Hi Sean,

Few more queries. Can you please share how your GPMC writes are happening? GPMC writes are interrupt based or polling based? 
Also, can you please mention which SDK you are using?

Regards,
Parth

Hi Parth,

Our GPMC writes are simply DSP pointer accesses to memory locations corresponding to CS0 of GPMC (0x14000000) base. I'm not sure I understand your interrupt vs polling based question. The GPMC is being used to perform memory mapped accesses of an FPGA with fixed timing characteristics. We use the GPMC CSL to configure it. Also, we are using Processor SDK 6.1.0.8.

Hi Sean,

Apologies for the delay.
Can you please share the code snippet where you are configuring the tasks that handles GPMC writes?

Regards,
Parth

Hi Parth,

We would rather not post important parts of our code on the forum. Would you be able to provide a way to share the code with you directly? Thanks!

Hi Sean,

I have sent you a request on e2e. Please accept that and we can have conversation there.

Regards,
Parth

Hi Sean,

Let's continue this discussion offline.

Regards,
Parth

Hi Sean,

Reopening this ticket for discussion. Please mention the current status of the issue.

Regards,
Parth

Hi Parth,

This situation is completely unchanged from when we left off before. There is a private message between us containing our source code. Thank you.

Hi Sean,

From the private message that you shared. There are two Hwi Tasks that can interrupt your low priority task. Have you tried disabling one of them and check if the other one is still delayed?

Sean DeHarde said:

We have noticed that if the HWI from the Mailbox comes in during the GPMC writes, the ISR of the high priority thread is significantly delayed.

Also, is this always the case or does it happens only sometimes?

Regards,
Parth

Hi,

Can you please share a little more details here. What application are you running? Is it from the PDK or it's a custom application?

Regards,
Parth